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IO, FBC updates to enable ABUS for Fleetwood
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Attributes:
-------------------------------------------------------------------------------

nest_attributes.xml
  add ATTR_LINK_TRAIN, written by platform on X, O endpoints to specify
    whether half or full link should be trained
  add ATTR_PROC_FABRIC_LINK_ACTIVE, written by p9_fbc_eff_config_links
  adjust enums for ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG, written
    by p9_fbc_eff_config_links
  add ATTR_PROC_FABRIC_[XA]_LINKS_CNFG, written by p9_fbc_eff_config_links

pervasive_attributes.xml
  create ATTR_PROC_NPU_REGION_ENABLED to encapsulate accessibility of
    NPU logic domain, written by p9_chiplet_scominit

chip_ec_attributes.xml
  add EC feature attribute controlling DL training workaround

Initfiles:
-------------------------------------------------------------------------------

p9.fbc.ab_hp.scom.initfile
  add logic to permit reset of chg_rate master dials in second phase SMP build
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums

p9.fbc.cd_hp.scom.initfile
p9.fbc.no_hp.scom.initfile
  consume number of configured X/A links from new attribute, simple addition
    won't work any longer given new ATTACHED_CHIP_CNFG enums

p9.fbc.ioe_dl.scom.initfile
  support half-link operation, based on ATTR_LINK_TRAIN on X endpoint target

p9.fbc.ioe_tl.scom.initifle
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums

p9.fbc.ioo_dl.scom.initfile
  support half-link operation, based on ATTR_LINK_TRAIN on O endpoint target
  qualify OLL enablement based on use as active fabric link
  adjust PHY training parameters based on current lab learning

p9.fbc.ioo_tl.scom.initfile
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
  support half-link operation, based on ATTACHED_CHIP_CNFG
  qualify TOD_ENABLE to apply only to O links carrying X traffic

p9.npu.scom.initfile
  clear OPTICAL_IO_CONFIG when not actively using NVLINK, finer-grained
    updates needed to support mix of O SMP and NVLINK usage

HWPs:
-------------------------------------------------------------------------------

p9_io_obus_dccal
  execute only on links actively carrying fabric protocol

p9_io_obus_linktrain
p9_io_regs
  encapsulate PHY FIFO reset sequence needed prior to FBC DL training execution

p9_chiplet_scominit
p9_npu_scominit
  partial good updates for NPU region

p9_fab_iovalid
  adjust iovalid manipulation/checking, as well as link delay reporting, to
    support half-link configuration

p9_smp_link_layer
  support half-link configuration via ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG
  implement OBUS PHY specific workarounds

p9_eff_config_links
  update ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG to support half-link
    configuration
  write ATTR_PROC_FABRIC_LINK_ACTIVE on X/O endpoint targets
  write ATTR_PROC_FABRIC_[XA]_LINKS_CNFG to reflect total number of logically
    configured links, for initfile consumption

Istep wrappers:
-------------------------------------------------------------------------------

p9_build_smp_wrap
  correctly loop over all system targets for second phase SMP build

p9_sys_chiplet_scominit_wrap
  initial release

Change-Id: I0d608f5fcf2dac35ecd7bc24a94006531cf31e0d
Original-Change-Id: Ic1d87df4d3ff0feca7ac2437fa61b6d2fc4a2d68
CQ: HW419022
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59108
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jjmcgill @dcrowell77
jjmcgill authored and dcrowell77 committed May 26, 2018
1 parent be6b655 commit 22160ff
Showing 1 changed file with 106 additions and 22 deletions.
128 changes: 106 additions & 22 deletions src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,6 @@
//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
// EXTFIR/RAS FIR field constants
const uint8_t IOVALID_FIELD_NUM_BITS = 2;

// DL FIR register field constants
const uint8_t DL_FIR_LINK0_TRAINED_BIT = 0;
Expand All @@ -70,10 +68,6 @@ const uint64_t DL_ERR1_STATUS_REG_OFFSET = 0x17;
const uint64_t DL_STATUS_REG_OFFSET = 0x28;
const uint64_t DL_ERR_MISC_REG_OFFSET = 0x29; // Optical only

// TL FIR register field constants
const uint8_t TL_FIR_TRAINED_FIELD_LENGTH = 2;
const uint8_t TL_FIR_TRAINED_LINK_TRAINED = 0x3;

// TL Link Delay register field constants
const uint8_t TL_LINK_DELAY_FIELD_NUM_BITS = 12;

Expand Down Expand Up @@ -464,10 +458,12 @@ fapi2::ReturnCode p9_fab_iovalid_link_validate(
FAPI_DBG("Start");
fapi2::buffer<uint64_t> l_dl_fir_reg;
fapi2::buffer<uint64_t> l_tl_fir_reg;
uint8_t l_tl_fir_trained_state = 0;
fapi2::Target<T> l_loc_endp_target;
fapi2::Target<T> l_rem_endp_target;
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_rem_chip_target;
fapi2::ATTR_LINK_TRAIN_Type l_loc_link_train;
bool l_dl_trained = false;
bool l_tl_trained = false;

// obtain link endpoints for FFDC
FAPI_TRY(p9_fab_iovalid_get_link_endpoints(i_target,
Expand All @@ -478,17 +474,36 @@ fapi2::ReturnCode p9_fab_iovalid_link_validate(
l_rem_chip_target),
"Error from p9_fab_iovalid_get_link_endpoints");

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LINK_TRAIN,
l_loc_endp_target,
l_loc_link_train),
"Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN)");

// validate DL training state
FAPI_TRY(fapi2::getScom(i_target, i_loc_link_ctl.dl_fir_addr, l_dl_fir_reg),
"Error from getScom (0x%.16llX)", i_loc_link_ctl.dl_fir_addr);

FAPI_ASSERT(l_dl_fir_reg.getBit<DL_FIR_LINK0_TRAINED_BIT>() &&
l_dl_fir_reg.getBit<DL_FIR_LINK1_TRAINED_BIT>(),
if (l_loc_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH)
{
l_dl_trained = l_dl_fir_reg.getBit<DL_FIR_LINK0_TRAINED_BIT>() &&
l_dl_fir_reg.getBit<DL_FIR_LINK1_TRAINED_BIT>();
}
else if (l_loc_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY)
{
l_dl_trained = l_dl_fir_reg.getBit<DL_FIR_LINK0_TRAINED_BIT>();
}
else
{
l_dl_trained = l_dl_fir_reg.getBit<DL_FIR_LINK1_TRAINED_BIT>();
}

FAPI_ASSERT(l_dl_trained,
fapi2::P9_FAB_IOVALID_DL_NOT_TRAINED_ERR()
.set_TARGET(i_target)
.set_LOC_ENDP_TARGET(l_loc_endp_target)
.set_LOC_ENDP_TYPE(i_loc_link_ctl.endp_type)
.set_LOC_ENDP_UNIT_ID(i_loc_link_ctl.endp_unit_id)
.set_LOC_LINK_TRAIN(l_loc_link_train)
.set_REM_ENDP_TARGET(l_rem_endp_target)
.set_REM_ENDP_TYPE(i_rem_link_ctl.endp_type)
.set_REM_ENDP_UNIT_ID(i_rem_link_ctl.endp_unit_id),
Expand All @@ -497,17 +512,28 @@ fapi2::ReturnCode p9_fab_iovalid_link_validate(
// validate TL training state
FAPI_TRY(fapi2::getScom(i_target, i_loc_link_ctl.tl_fir_addr, l_tl_fir_reg),
"Error from getScom (0x%.16llX)", i_loc_link_ctl.tl_fir_addr);
FAPI_TRY(l_tl_fir_reg.extractToRight(l_tl_fir_trained_state,
i_loc_link_ctl.tl_fir_trained_field_start_bit,
TL_FIR_TRAINED_FIELD_LENGTH),
"Error extracting TL layer training state");

FAPI_ASSERT(l_tl_fir_trained_state == TL_FIR_TRAINED_LINK_TRAINED,
if (l_loc_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH)
{
l_tl_trained = l_tl_fir_reg.getBit(i_loc_link_ctl.tl_fir_trained_field_start_bit) &&
l_tl_fir_reg.getBit(i_loc_link_ctl.tl_fir_trained_field_start_bit + 1);
}
else if (l_loc_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY)
{
l_tl_trained = l_tl_fir_reg.getBit(i_loc_link_ctl.tl_fir_trained_field_start_bit);
}
else
{
l_tl_trained = l_tl_fir_reg.getBit(i_loc_link_ctl.tl_fir_trained_field_start_bit + 1);
}

FAPI_ASSERT(l_tl_trained,
fapi2::P9_FAB_IOVALID_TL_NOT_TRAINED_ERR()
.set_TARGET(i_target)
.set_LOC_ENDP_TARGET(l_loc_endp_target)
.set_LOC_ENDP_TYPE(i_loc_link_ctl.endp_type)
.set_LOC_ENDP_UNIT_ID(i_loc_link_ctl.endp_unit_id)
.set_LOC_LINK_TRAIN(l_loc_link_train)
.set_REM_ENDP_TARGET(l_rem_endp_target)
.set_REM_ENDP_TYPE(i_rem_link_ctl.endp_type)
.set_REM_ENDP_UNIT_ID(i_rem_link_ctl.endp_unit_id),
Expand Down Expand Up @@ -543,12 +569,14 @@ fapi_try_exit:
///
/// @param[in] i_target Processor chip target
/// @param[in] i_link_ctl X/A link control structure for link
/// @param[in] i_link_train Sublinks to monitor
/// @param[out] o_link_delay Link delay
///
/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
fapi2::ReturnCode p9_fab_iovalid_get_link_delay(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9_fbc_link_ctl_t& i_link_ctl,
const fapi2::ATTR_LINK_TRAIN_Type i_link_train,
uint32_t o_link_delay)
{
FAPI_DBG("Start");
Expand All @@ -566,7 +594,23 @@ fapi2::ReturnCode p9_fab_iovalid_get_link_delay(
i_link_ctl.tl_link_delay_lo_start_bit,
TL_LINK_DELAY_FIELD_NUM_BITS),
"Error extracting link delay (lo)");
o_link_delay = (l_sublink_delay[0] + l_sublink_delay[1]) / 2;

if (i_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH)
{
o_link_delay = (l_sublink_delay[0] + l_sublink_delay[1]) / 2;
}
else if (i_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY)
{
o_link_delay = l_sublink_delay[0];
}
else if (i_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY)
{
o_link_delay = l_sublink_delay[1];
}
else
{
o_link_delay = 0xFFFFFFFF;
}

fapi_try_exit:
FAPI_DBG("End");
Expand Down Expand Up @@ -598,6 +642,8 @@ fapi2::ReturnCode p9_fab_iovalid_get_link_delays(
fapi2::Target<T> l_loc_endp_target;
fapi2::Target<T> l_rem_endp_target;
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_rem_chip_target;
fapi2::ATTR_LINK_TRAIN_Type l_loc_link_train;
fapi2::ATTR_LINK_TRAIN_Type l_rem_link_train;

// get link endpoint targets
FAPI_TRY(p9_fab_iovalid_get_link_endpoints(
Expand All @@ -611,15 +657,27 @@ fapi2::ReturnCode p9_fab_iovalid_get_link_delays(

// read link delay from local/remote chip targets
// link control structures provide register/bit offsets to collect
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LINK_TRAIN,
l_loc_endp_target,
l_loc_link_train),
"Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN, local)");

FAPI_TRY(p9_fab_iovalid_get_link_delay(
i_loc_chip_target,
i_loc_link_ctl,
l_loc_link_train,
l_loc_link_delay),
"Error from p9_fab_iovalid_get_link_delay (local)");

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LINK_TRAIN,
l_rem_endp_target,
l_rem_link_train),
"Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN, remote)");

FAPI_TRY(p9_fab_iovalid_get_link_delay(
l_rem_chip_target,
i_rem_link_ctl,
l_rem_link_train,
l_rem_link_delay),
"Error from p9_fab_iovalid_get_link_delay (remote)");

Expand All @@ -638,13 +696,15 @@ fapi_try_exit:
/// @param[in] i_target Reference to processor chip target
/// @param[in] i_ctl Reference to link control structure
/// @param[in] i_set_not_clear Define iovalid operation (true=set, false=clear)
/// @param[in] i_en Defines sublinks to enable
///
/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode
p9_fab_iovalid_update_link(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9_fbc_link_ctl_t& i_ctl,
const bool i_set_not_clear)
const bool i_set_not_clear,
const uint8_t i_en)
{
FAPI_DBG("Start");

Expand All @@ -657,8 +717,19 @@ p9_fab_iovalid_update_link(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
{
// set iovalid
l_iovalid_mask.flush<0>();
FAPI_TRY(l_iovalid_mask.setBit(i_ctl.iovalid_field_start_bit,
IOVALID_FIELD_NUM_BITS));

if ((i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_EVEN_ONLY))
{
FAPI_TRY(l_iovalid_mask.setBit(i_ctl.iovalid_field_start_bit));
}

if ((i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_ODD_ONLY))
{
FAPI_TRY(l_iovalid_mask.setBit(i_ctl.iovalid_field_start_bit + 1));
}

// clear RAS FIR mask
l_ras_fir_mask.flush<1>();
FAPI_TRY(l_ras_fir_mask.clearBit(i_ctl.ras_fir_field_bit));
Expand All @@ -681,8 +752,19 @@ p9_fab_iovalid_update_link(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
{
// clear iovalid
l_iovalid_mask.flush<1>();
FAPI_TRY(l_iovalid_mask.clearBit(i_ctl.iovalid_field_start_bit,
IOVALID_FIELD_NUM_BITS));

if ((i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_EVEN_ONLY))
{
FAPI_TRY(l_iovalid_mask.clearBit(i_ctl.iovalid_field_start_bit));
}

if ((i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_ODD_ONLY))
{
FAPI_TRY(l_iovalid_mask.clearBit(i_ctl.iovalid_field_start_bit + 1));
}

// set RAS FIR mask
l_ras_fir_mask.flush<0>();
FAPI_TRY(l_ras_fir_mask.setBit(i_ctl.ras_fir_field_bit));
Expand Down Expand Up @@ -760,7 +842,8 @@ p9_fab_iovalid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
FAPI_DBG("Updating link X%d", l_link_id);
FAPI_TRY(p9_fab_iovalid_update_link(i_target,
P9_FBC_XBUS_LINK_CTL_ARR[l_link_id],
i_set_not_clear),
i_set_not_clear,
l_x_en[l_link_id]),
"Error from p9_fab_iovalid_update_link (X)");

if (i_set_not_clear)
Expand Down Expand Up @@ -816,7 +899,8 @@ p9_fab_iovalid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
FAPI_DBG("Updating link A%d", l_link_id);
FAPI_TRY(p9_fab_iovalid_update_link(i_target,
P9_FBC_ABUS_LINK_CTL_ARR[l_link_id],
i_set_not_clear),
i_set_not_clear,
l_a_en[l_link_id]),
"Error from p9_fab_iovalid_update_link (A)");

if (i_set_not_clear)
Expand Down

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