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P9 Centaur Erepair Update
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- Updated Centaur Procedures to reference EDI registers

Change-Id: I138e13da1bd6f684a2c9be5989b9a3620ae953ae
CQ: SW439818
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63312
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63318
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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@steffenchris
steffenchris authored and Nicholas E. Bofferding committed Aug 3, 2018
1 parent f5db0c7 commit 24188d2
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Showing 4 changed files with 33 additions and 28 deletions.
30 changes: 16 additions & 14 deletions src/import/chips/centaur/procedures/hwp/io/p9_io_cen_pdwn_lanes.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -116,7 +116,7 @@ fapi2::ReturnCode rx_pdwn_lanes(
const std::vector< uint8_t >& i_bad_lanes)
{
const uint8_t GRP0 = 0;
FAPI_DBG("rx_pdwn_lanes: Enter Size(%d)", i_bad_lanes.size());
FAPI_IMP("rx_pdwn_lanes: Enter Size(%d)", i_bad_lanes.size());
char target_string[fapi2::MAX_ECMD_STRING_LEN];
fapi2::toString(i_target, target_string, fapi2::MAX_ECMD_STRING_LEN);

Expand All @@ -131,11 +131,13 @@ fapi2::ReturnCode rx_pdwn_lanes(
GRP0,
i_bad_lanes[index]);

FAPI_TRY(io::rmw(EDIP_RX_LANE_DIG_PDWN, i_target, GRP0, i_bad_lanes[index], 1),
"Failed rmw rx dig pdwn reg");
FAPI_TRY(io::rmw(EDI_RX_LANE_PDWN, i_target, GRP0, i_bad_lanes[index], 1),
"Failed rmw rx pdwn reg");

// Set rx_wt_lane_disabled for this lane; see SW244284, SW280992
FAPI_TRY(io::rmw(EDI_RX_WT_LANE_DISABLED, i_target, GRP0, i_bad_lanes[index], 1),
"Failed rmw rx wt lane disabled reg");

FAPI_TRY(io::rmw(EDIP_RX_LANE_ANA_PDWN, i_target, GRP0, i_bad_lanes[index], 1),
"Failed rmw rx ana pdwn reg");

}
}
Expand Down Expand Up @@ -170,15 +172,15 @@ fapi2::ReturnCode tx_pdwn_lanes(

if(!i_bad_lanes.empty())
{
FAPI_TRY(io::read(EDIP_TX_MSBSWAP, i_target, GRP0, LN0, l_data),
"Failed read edip_tx_msbswap");
l_msbswap = io::get(EDIP_TX_MSBSWAP, l_data);
FAPI_TRY(io::read(EDI_TX_MSBSWAP, i_target, GRP0, LN0, l_data),
"Failed read edi_tx_msbswap");
l_msbswap = io::get(EDI_TX_MSBSWAP, l_data);

if(l_msbswap == 0x1)
{
FAPI_TRY(io::read(EDIP_TX_END_LANE_ID, i_target, GRP0, LN0, l_data));
l_end_lane = io::get(EDIP_TX_END_LANE_ID, l_data);
FAPI_DBG("edip_tx_msbswap: tx_end_lane_id(%d).", l_end_lane);
FAPI_TRY(io::read(EDI_TX_END_LANE_ID, i_target, GRP0, LN0, l_data));
l_end_lane = io::get(EDI_TX_END_LANE_ID, l_data);
FAPI_DBG("edi_tx_msbswap: tx_end_lane_id(%d).", l_end_lane);
}

for(uint8_t index = 0; index < i_bad_lanes.size(); ++index)
Expand All @@ -188,7 +190,7 @@ fapi2::ReturnCode tx_pdwn_lanes(
if(l_msbswap == 0x1)
{
l_lane = l_end_lane - i_bad_lanes[index];
FAPI_DBG("edip_tx_msbswap: tx_end_lane_id(%d) lane(%d -> %d).",
FAPI_DBG("edi_tx_msbswap: tx_end_lane_id(%d) lane(%d -> %d).",
l_end_lane, i_bad_lanes[index], l_lane);
}

Expand All @@ -199,7 +201,7 @@ fapi2::ReturnCode tx_pdwn_lanes(
GRP0,
l_lane);

FAPI_TRY(io::rmw(EDIP_TX_LANE_PDWN, i_target, GRP0, l_lane, 1));
FAPI_TRY(io::rmw(EDI_TX_LANE_PDWN, i_target, GRP0, l_lane, 1));

}
}
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15 changes: 7 additions & 8 deletions src/import/chips/centaur/procedures/hwp/io/p9_io_cen_read_erepair.C
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Original file line number Diff line number Diff line change
Expand Up @@ -83,26 +83,25 @@ fapi2::ReturnCode p9_io_cen_read_erepair(

o_bad_lanes.clear();

// TODO CHANGE TO EDI REGISTERS
FAPI_TRY(io::read(EDIP_RX_GLBSM_STAT9_E_PG, i_target, GRP0, LN0, l_data),
FAPI_TRY(io::read(EDI_RX_BAD_LANE_ENC_GCRMSG_PG, i_target, GRP0, LN0, l_data),
"Reading Bad Lane Code Failed.");

FAPI_DBG("Bad Lane Code: %d", io::get(EDIP_RX_BAD_LANE_CODE, l_data));
FAPI_DBG("Bad Lane Code: %d", io::get(EDI_RX_BAD_LANE_CODE_GCRMSG, l_data));

switch(io::get(EDIP_RX_BAD_LANE_CODE, l_data))
switch(io::get(EDI_RX_BAD_LANE_CODE_GCRMSG, l_data))
{
case BAD_LANES_3PLUS:
FAPI_DBG("Bad Lane: Three or more bad lanes found.");

// We will intentionally fall through to collect bad lane 1 & 2.
case BAD_LANES_2:
FAPI_DBG("Bad Lane 2: %d", io::get(EDIP_RX_BAD_LANE2, l_data));
o_bad_lanes.push_back((uint8_t)io::get(EDIP_RX_BAD_LANE2, l_data));
FAPI_DBG("Bad Lane 2: %d", io::get(EDI_RX_BAD_LANE2_GCRMSG, l_data));
o_bad_lanes.push_back((uint8_t)io::get(EDI_RX_BAD_LANE2_GCRMSG, l_data));

// We will intentionally fall through to collect bad lane 1.
case BAD_LANES_1:
FAPI_DBG("Bad Lane 1: %d", io::get(EDIP_RX_BAD_LANE1, l_data));
o_bad_lanes.push_back((uint8_t)io::get(EDIP_RX_BAD_LANE1, l_data));
FAPI_DBG("Bad Lane 1: %d", io::get(EDI_RX_BAD_LANE1_GCRMSG, l_data));
o_bad_lanes.push_back((uint8_t)io::get(EDI_RX_BAD_LANE1_GCRMSG, l_data));
break;

case BAD_LANES_0:
Expand Down
10 changes: 5 additions & 5 deletions src/import/chips/centaur/procedures/hwp/io/p9_io_cen_restore_erepair.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -136,17 +136,17 @@ fapi2::ReturnCode set_rx_bad_lane_vectors(
// to GCR registers only being 16 bits wide.
if(i_bad_lanes[index] < IO_GCR_REG_WIDTH)
{
FAPI_TRY(io::read(EDIP_RX_LANE_BAD_VEC_0_15, i_target, GRP0, LN0, l_data));
FAPI_TRY(io::read(EDI_RX_LANE_BAD_VEC_0_15, i_target, GRP0, LN0, l_data));
l_data |= (0x8000 >> bad_lane);
FAPI_TRY(io::write(EDIP_RX_LANE_BAD_VEC_0_15, i_target, GRP0, LN0, l_data));
FAPI_TRY(io::write(EDI_RX_LANE_BAD_VEC_0_15, i_target, GRP0, LN0, l_data));
}
else
{
bad_lane -= IO_GCR_REG_WIDTH;

FAPI_TRY(io::read(EDIP_RX_LANE_BAD_VEC_16_23, i_target, GRP0, LN0, l_data));
FAPI_TRY(io::read(EDI_RX_LANE_BAD_VEC_16_31, i_target, GRP0, LN0, l_data));
l_data |= (0x8000 >> bad_lane);
FAPI_TRY(io::write(EDIP_RX_LANE_BAD_VEC_16_23, i_target, GRP0, LN0, l_data));
FAPI_TRY(io::write(EDI_RX_LANE_BAD_VEC_16_31, i_target, GRP0, LN0, l_data));
}

}
Expand Down
6 changes: 5 additions & 1 deletion src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -256,7 +256,11 @@
#define EDI_TX_ZCAL_REQ 0x800f04000000003f, 49, 1 // impedance calibration sequence enable\r\n\t rising edge initiates calibration seqeunce and clears all status. tx_zcal_done indicates completion and valid results available(default)\r\n\t0:(disabled) inactive. must be set prior to enable. \r\n\t1:(enabled) enable.\r\n\tjfg
#define EDI_TX_ZCAL_DONE 0x800f04000000003f, 50, 1 // impedance calibration sequence complete\r\n\t results are valid when 1.\r\n\tjfg
#define EDI_TX_ZCAL_ERROR 0x800f04000000003f, 51, 1 // impedance calibration sequence error\r\n\t indicates, independent of tx_zcal_done, whether no calibration answer was found, or state machine failed. cleared on tx_zcal_req.\r\n\tjfg

#define EDI_TX_LANE_PDWN 0x800404000000003f, 48, 1 // used to drive inhibit (tristate) and fully power down a lane independent of the logical lane disable. this control is independent from the per-group logical lane disable settings (tx_lane_disable_vec*) in order to allow for flexibility. note that this control routes through the boundary scan logic, which has dominance. also note that per-group registers tx_lane_disabled_vec_0_15 and tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. note that this per-lane register is adjusted for lane swizzling automatically in hw but it is not adjusted automatically in hw when in the msb-lsb swap mode so the erepair procedure needs to take care to power down the correct lane when in this mode. \r\n\t0:(enabled) lane powered up (default)\r\n\t1:(disabled) lane drive inhibited (tristated) and powered down. the lane_disable_vec_* per-group registers configure the state machine but do not automatically power down or tristate the lanes. debug note: you have to account for swizzle when correlating the per-pack latch to the per-group latch setting.\r\n\tmbs
#define EDI_TX_END_LANE_ID 0x800ca4000000003f, 57, 7 // this field is used to programmably set the last lane position in the group but relative to the bus.\r\n\tdmb
#define EDI_TX_MSBSWAP 0x800c1c000000003f, 53, 1 // used to enable end-for-end or msb swap of tx lanes. for example, lanes 0 and n-1 swap, lanes 1 and n-2 swap, etc. \r\n\t0:(nomsbswap) no swap (default)\r\n\t1:(msbswap) end-for-end swap mode\r\n\tmbs
#define EDI_RX_LANE_PDWN 0x800000000000003f, 48, 1 // used to receive inhibit and fully power down a lane independent of the logical lane disable. this control is independent from the per-group logical lane disable settings (rx_lane_disable_vec*) in order to allow for flexibility. note that this control routes through the boundary scan logic, which has dominance. also note that per-group registers rx_lane_disabled_vec_0_15 and rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. note that this per-lane register is adjusted for lane swizzling automatically in hw but it is not adjusted automatically in hw when in the msb-lsb swap mode so the erepair procedure needs to take care to power down the correct lane when in this mode. \r\n\t0:(enabled) lane powered up (default)\r\n\t1:(disabled) lane receive inhibited and powered down. the lane_disable_vec_* per-group registers configure the state machine but do not automatically power down or tristate the lanes. debug note: you have to account for swizzle when correlating the per-pack latch to the per-group latch setting.\r\n\tmbs
#define EDI_RX_WT_LANE_DISABLED 0x8000f0000000003f, 48, 1 // wiretest has disabled this lane\r\n\trjr



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