reverting FIRs to master values, setting only bit 8

Change-Id: I9ff37faffad1c6c2323c501a5c55992a81fc9fd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35575 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36492 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
open-power · Feb 17, 2017 · 258d507 · 258d507
1 parent d1d4d9e
commit 258d507
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diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
@@ -32,6 +32,8 @@ using namespace fapi2;
 constexpr uint64_t literal_0x00200102000D7FFF = 0x00200102000D7FFF;
 constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000;
 constexpr uint64_t literal_0x00DF0201C0000000 = 0x00DF0201C0000000;
+constexpr uint64_t literal_0x80000000 = 0x80000000;
+constexpr uint64_t literal_0x8000000 = 0x8000000;
 constexpr uint64_t literal_0x1 = 0x1;
 
 fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0,
@@ -61,6 +63,18 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             l_scom_buffer.insert<0, 54, 0, uint64_t>(literal_0x00DF0201C0000000 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x3011807ull, l_scom_buffer));
         }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x301180aull, l_scom_buffer ));
+
+            l_scom_buffer.insert<8, 31, 33, uint64_t>(literal_0x80000000 );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x301180aull, l_scom_buffer));
+        }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x301180bull, l_scom_buffer ));
+
+            l_scom_buffer.insert<8, 28, 36, uint64_t>(literal_0x8000000 );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x301180bull, l_scom_buffer));
+        }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x301184dull, l_scom_buffer ));
 

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2090,6 +2090,25 @@
       </chip>
     </chipEcFeature>
   </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW395939</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      For DD1, VAS has no BAR disable bit.  Adding attribute to enable non zero
+      init for the MMIO BARs. Issue HW395939
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->
   <!-- ******************************************************************** -->