P9A Tx Fifo Init + Init Settings Update

- Added Tx Fifo Init Function to Dccal
- Forced rx_dc_enable_cm_coarse_en = 0
- Updated P9A Filt Pll Attribute to select BG = 0

Change-Id: I7090856ba48886fb278e65814249a0166b7fe098
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80218
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80251
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C

@@ -250,6 +250,14 @@ fapi2::ReturnCode p9a_omic_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>&
             (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF );
             FAPI_TRY(fapi2::putScom(TGT0, 0x800970000701103full, l_scom_buffer));
         }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x800978000701103full, l_scom_buffer ));
+
+            constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF = 0x0;
+            l_scom_buffer.insert<48, 1, 63, uint64_t>
+            (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF );
+            FAPI_TRY(fapi2::putScom(TGT0, 0x800978000701103full, l_scom_buffer));
+        }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800988000701103full, l_scom_buffer ));
 

src/import/chips/p9/procedures/hwp/io/p9a_io_omi_dccal.C

@@ -722,6 +722,46 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+/**
+ * @brief Init PHY Tx FIFO Logic
+ * @param[in] i_tgt         FAPI2 Target
+ * @param[in] i_lave_vector Lanve Vector
+ * @retval ReturnCode
+ */
+fapi2::ReturnCode p9_omi_tx_fifo_init(const OMIC_TGT i_tgt, const uint32_t i_lane_vector)
+{
+    FAPI_IMP("p9_omi_tx_fifo_init: I/O OMI Entering");
+    const uint8_t GRP0  = 0;
+    const uint8_t LANES = 24;
+    fapi2::buffer<uint64_t> l_data = 0;
+
+    // Power up Per-Lane Registers
+    for(uint8_t l_lane = 0; l_lane < LANES; ++l_lane)
+    {
+        if(((0x1 << l_lane) & i_lane_vector) != 0)
+        {
+            // - Clear TX_UNLOAD_CLK_DISABLE
+            FAPI_TRY(io::read(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data));
+            io::set(OPT_TX_UNLOAD_CLK_DISABLE, 0, l_data);
+            FAPI_TRY(io::write(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data));
+
+            // - Set TX_FIFO_INIT
+            l_data.flush<0>();
+            io::set(OPT_TX_FIFO_INIT, 1, l_data);
+            FAPI_TRY(io::write(OPT_TX_CNTL1G_PL, i_tgt, GRP0, l_lane, l_data));
+
+            // - Set TX_UNLOAD_CLK_DISABLE
+            FAPI_TRY(io::read(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data));
+            io::set(OPT_TX_UNLOAD_CLK_DISABLE, 1, l_data );
+            FAPI_TRY(io::write(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data));
+        }
+    }
+
+fapi_try_exit:
+    FAPI_IMP("p9_omi_tx_fifo_init: I/O OMI Exiting");
+    return fapi2::current_err;
+}
+
 } // end namespace P9A_IO_OMI_DCCAL
 
 using namespace P9A_IO_OMI_DCCAL;
@@ -784,6 +824,9 @@ fapi2::ReturnCode p9a_io_omi_dccal(const OMIC_TGT i_tgt, const uint32_t i_lane_v
     FAPI_TRY(set_omi_flywheel_off(i_tgt, i_lane_vector, 0));
     FAPI_TRY(set_omi_pr_edge_track_cntl(i_tgt, i_lane_vector, 0));
 
+    // Run Tx FIFO Init
+    FAPI_TRY(p9_omi_tx_fifo_init(i_tgt, i_lane_vector));
+
 fapi_try_exit:
     FAPI_IMP("p9_io_omi_dccal: I/O OMI Exiting");
     return fapi2::current_err;

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -1265,13 +1265,6 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_AXONE</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
     </chipEcFeature>
   </attribute>
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