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INTRP HW Workaround for Clockgating Issue
- The issue occurs because the slave procs route their interrupts to the master proc, which forces the LSI Interrupt event over the PSIHB. However, the master is still using the local wire for its LSI Interrupt events. There is a situation where undesirable hw behavior can occur because of this (dropped/missed interrupts) - This workaround will set the ESB Notification Register on the master proc, which will force the lsi interrupts over the PSIHB and not the local wire. Change-Id: If595f62d268b6ac504f714b7e50e452b9f926015 CQ: SW441117 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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