Add extra DRAM reset after RCD load on Nimbus

Change-Id: Id5d6a6d8e98c93dadbeafda9e061f9b1fbdcd64f CQ:SW430241 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59071 Dev-Ready: Louis Stermole <stermole@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59080 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
open-power · May 28, 2018 · 264b8c7 · 264b8c7
1 parent dd251ca
commit 264b8c7
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Showing 2 changed files with 7 additions and 4 deletions.
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -129,6 +129,10 @@ fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
               "Failed to load 4-bit RC09 control word for %s",
               mss::c_str(i_target));
 
+    // Toggle RC06 again to ensure the DRAM is reset properly
+    FAPI_TRY( mss::workarounds::rcw_reset_dram(i_target, io_inst), "%s failed to add reset workaround functionality",
+              mss::c_str(i_target));
+
 fapi_try_exit:
     return fapi2::current_err;
 }

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C
@@ -62,9 +62,8 @@ fapi2::ReturnCode rcw_reset_dram( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
     constexpr uint64_t RESET_CW = 6;
     constexpr uint64_t RESET_DRAM = 0x02;
     constexpr uint64_t CLEAR_RESET = 0x03;
-    // Using a delay of 2000 cycles to ensure we're holding everything for a long enough time
-    // Note: this value is set using "engineering judgement" and was considered arbitrarily high enough
-    constexpr uint64_t DELAY = 2000;
+    // Note: the minimum for a FORC06 soft reset is 32 cycles, but we empirically tested it at 8k cycles
+    constexpr uint64_t DELAY = 8000;
     // Function space 0
     constexpr uint8_t FS0 = 0;