Moves conversions to be in the generic code space

Change-Id: Id0270a97066a06615b165ccd8c84e444d134394e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63845 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64048 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
open-power · Aug 20, 2018 · 28b8367 · 28b8367
1 parent 1b5a02c
commit 28b8367
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diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
@@ -37,7 +37,7 @@
 #include <p9_mc_scom_addresses.H>
 
 #include <generic/memory/lib/utils/c_str.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/eff_config/timing.H>
 #include <lib/ccs/ccs.H>
 #include <lib/dimm/bcw_load_ddr4.H>

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
@@ -47,7 +47,7 @@
 #include <lib/mcbist/memdiags.H>
 #include <lib/mcbist/mcbist.H>
 #include <lib/mcbist/settings.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 
 #include <lib/mc/port.H>
 #include <lib/phy/dp16.H>

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
@@ -41,7 +41,7 @@
 #include <lib/eff_config/timing.H>
 #include <lib/dimm/ddr4/mrs_load_ddr4.H>
 #include <lib/dimm/rank.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <generic/memory/lib/utils/find.H>
 #include <lib/dimm/eff_dimm.H>
 #include <lib/dimm/mrs_load.H>
@@ -2627,21 +2627,29 @@ fapi2::ReturnCode eff_dimm::dram_cwl()
     // Using an if branch because a ternary conditional wasn't working with params for find_value_from_key
     if (l_preamble == 0)
     {
-        FAPI_TRY( mss::find_value_from_key( CWL_TABLE_1,
-                                            iv_freq,
-                                            l_cwl),
-                  "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
-                  iv_freq,
-                  l_preamble);
+        FAPI_ASSERT( mss::find_value_from_key( CWL_TABLE_1,
+                                               iv_freq,
+                                               l_cwl),
+                     fapi2::MSS_DRAM_CWL_ERROR()
+                     .set_TARGET(iv_mca)
+                     .set_FREQ(iv_freq)
+                     .set_PREAMBLE(l_preamble),
+                     "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
+                     iv_freq,
+                     l_preamble);
     }
     else
     {
-        FAPI_TRY( mss::find_value_from_key( CWL_TABLE_2,
-                                            iv_freq,
-                                            l_cwl),
-                  "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
-                  iv_freq,
-                  l_preamble);
+        FAPI_ASSERT( mss::find_value_from_key( CWL_TABLE_2,
+                                               iv_freq,
+                                               l_cwl),
+                     fapi2::MSS_DRAM_CWL_ERROR()
+                     .set_TARGET(iv_mca)
+                     .set_FREQ(iv_freq)
+                     .set_PREAMBLE(l_preamble),
+                     "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d",
+                     iv_freq,
+                     l_preamble);
 
     }
 

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
@@ -37,9 +37,10 @@
 
 #include <cstdint>
 #include <fapi2.H>
+#include <lib/mss_attribute_accessors.H>
 #include <generic/memory/lib/utils/find.H>
 #include <generic/memory/lib/utils/shared/mss_generic_consts.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 
 namespace mss
 {
@@ -352,7 +353,7 @@ template< fapi2::TargetType T >
 inline uint64_t tmod( const fapi2::Target<T>& i_target )
 {
     // Per DDR4 Full spec update (79-4A) - timing requirements
-    return mss::max_ck_ns( i_target, 24, 15 );
+    return mss::max_ck_ns<T>( i_target, 24, 15 );
 }
 
 ///
@@ -410,7 +411,7 @@ inline uint64_t twlo_twloe(const fapi2::Target<T>& i_target)
     constexpr uint64_t l_dq_ck = 1;
     constexpr uint64_t l_dqs_ck = 1;
     uint8_t l_wlo_ck = 0;
-    uint64_t l_wloe_ck = mss::ns_to_cycles(i_target, 2);
+    uint64_t l_wloe_ck = mss::ns_to_cycles<T>(i_target, 2);
     uint64_t l_twlo_twloe = 0;
     uint8_t l_twldqsen = 0;
 
@@ -1151,7 +1152,7 @@ inline uint64_t tvrefdqe( const fapi2::Target<T>& i_target )
 {
     // JEDEC tVREFDQE in ns
     constexpr uint64_t tVREFDQE = 150;
-    return ns_to_cycles(i_target, tVREFDQE);
+    return ns_to_cycles<T>(i_target, tVREFDQE);
 }
 
 ///
@@ -1165,7 +1166,7 @@ inline uint64_t tvrefdqx( const fapi2::Target<T>& i_target )
 {
     // JEDEC tVREFDQX in ns
     constexpr uint64_t tVREFDQX = 150;
-    return ns_to_cycles(i_target, tVREFDQX);
+    return ns_to_cycles<T>(i_target, tVREFDQX);
 }
 
 ///

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H
@@ -46,7 +46,7 @@
 
 // mss lib
 #include <generic/memory/lib/spd/spd_facade.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/freq/sync.H>
 
 namespace mss

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C
@@ -447,7 +447,7 @@ fapi2::ReturnCode spd_supported_freq(const fapi2::Target<TARGET_TYPE_MCBIST>& i_
 
     // Get cached decoder
     std::vector< mss::spd::facade > l_spd_facades;
-    FAPI_TRY( get_spd_decoder_list(i_target, l_spd_facades) );
+    FAPI_TRY( get_spd_decoder_list(i_target, l_spd_facades), "%s get decoder - spd", mss::c_str(i_target) );
 
     // Looking for the biggest application period on an MC.
     // This will further reduce supported frequencies the system can run on.
@@ -470,7 +470,7 @@ fapi2::ReturnCode spd_supported_freq(const fapi2::Target<TARGET_TYPE_MCBIST>& i_
         l_largest_tck = std::max(l_largest_tck, l_tck_min_in_ps);
         l_largest_tck = std::min(l_largest_tck, l_tckmax_in_ps);
 
-        FAPI_TRY( mss::ps_to_freq(l_largest_tck, l_dimm_freq) );
+        FAPI_TRY( mss::ps_to_freq(l_largest_tck, l_dimm_freq), "%s ps to freq %lu", mss::c_str(i_target), l_largest_tck );
         FAPI_INF("Biggest freq supported from SPD %d MT/s for %s",
                  l_dimm_freq, mss::c_str(l_dimm));
 
@@ -503,9 +503,9 @@ fapi2::ReturnCode supported_freqs(const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar
     std::vector<uint8_t> l_deconfigured = {0};
 
     // Retrieve system MRW, SPD, and VPD constraints
-    FAPI_TRY( mss::max_allowed_dimm_freq(l_max_freqs.data()) );
-    FAPI_TRY( spd_supported_freq(i_target, l_spd_supported_freq) );
-    FAPI_TRY( vpd_supported_freqs(i_target, l_vpd_supported_freqs) );
+    FAPI_TRY( mss::max_allowed_dimm_freq(l_max_freqs.data()), "%s max_allowed_dimm_freq", mss::c_str(i_target) );
+    FAPI_TRY( spd_supported_freq(i_target, l_spd_supported_freq), "%s spd supported freqs", mss::c_str(i_target) );
+    FAPI_TRY( vpd_supported_freqs(i_target, l_vpd_supported_freqs), "%s vpd supported freqs", mss::c_str(i_target) );
 
     // Limit frequency scoreboard according to MRW constraints
     FAPI_TRY( limit_freq_by_mrw(i_target, l_max_freqs, l_scoreboard) );

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.H
@@ -39,6 +39,7 @@
 #include <vector>
 
 #include <fapi2.H>
+#include <lib/shared/mss_const.H>
 
 namespace mss
 {

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
@@ -41,7 +41,7 @@
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
 #include <lib/mss_attribute_accessors.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/shared/mss_const.H>
 #include <generic/memory/lib/utils/scom.H>
 #include <lib/dimm/rank.H>

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H
@@ -43,6 +43,7 @@
 
 #include <generic/memory/lib/utils/poll.H>
 #include <generic/memory/lib/utils/memory_size.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/shared/mss_const.H>
 #include <lib/utils/bit_count.H>
 #include <lib/utils/num.H>
@@ -418,6 +419,30 @@ class mcbistTraits<fapi2::TARGET_TYPE_MCS>
 
 };
 
+///
+/// @brief Return the estimated time an MCBIST subtest will take to complete
+/// Useful for initial polling delays, probably isn't accurate for much else
+/// as it doesn't take refresh in to account (which will necessarily slow down
+/// the program.)
+/// @param[in] i_target the target from which to gather memory frequency
+/// @param[in] i_bytes number of *bytes* in the address range
+/// @param[in] i_64B_per mss::YES if the command is 64B, mss::NO if it's 128B. Defaults to mss::YES
+/// @return the initial polling delay for this program in ns
+///
+template< fapi2::TargetType T >
+inline uint64_t calculate_initial_delay(const fapi2::Target<T>& i_target,
+                                        const uint64_t i_bytes,
+                                        const bool i_64B_per = mss::YES)
+{
+    // TODO RTC: 164104 Update MCBIST delay calculator. As we learn more about what
+    // the lab really needs, we can probably make this function better.
+    const uint64_t l_bytes_per_cmd = (i_64B_per == mss::YES) ? 64 : 128;
+
+    // Best case is a command takes 4 cycles. Given the number of commands and address space size
+    // we can get some idea of how long to wait before we start polling.
+    return cycles_to_ns(i_target, (i_bytes / l_bytes_per_cmd) * mss::CYCLES_PER_CMD);
+}
+
 namespace mcbist
 {
 

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
@@ -62,17 +62,9 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target,
     // i.e. DQS_ALIGN + INITIAL_PAT_WR = 3 polls, so this should be 2
     constexpr uint64_t MINIMUM_POLL_COUNT = 2;
 
-    // Sometimes when running in sim, particularly Mesa, it is helpful to not delay a bunch
-    // when training starts - makes it simpler to get an AET for, say, write leveling. So
-    // this is here to allow the simple removal of the initial delay for those situations.
-#ifdef THRASH_CCS_IP_IN_SIM
-    io_poll.iv_initial_delay = mss::cycles_to_ns(i_target, 1);
-    io_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(1);
-#else
     // We don't want to wait too long for the initial check, just some hueristics here
     io_poll.iv_initial_delay = mss::cycles_to_ns(i_target, i_total_cycles / 8);
     io_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(i_total_cycles / 8);
-#endif
 
     // Delay 10us between polls, and setup the poll count so
     // iv_initial_delay + (iv_delay * iv_poll_count) == i_total_cycles + some fudge;

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C
@@ -38,7 +38,7 @@
 #include <generic/memory/lib/utils/scom.H>
 #include <generic/memory/lib/utils/pos.H>
 #include <generic/memory/lib/utils/poll.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/workarounds/adr32s_workarounds.H>
 
 using fapi2::TARGET_TYPE_MCA;

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
@@ -321,8 +321,9 @@ uint64_t dqs_align::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA
     // This step runs for approximately 6 x 600 x 4 DRAM clocks per rank pair.
     const uint64_t l_dqs_align_cycles = 6 * 600 * 4;
 
-    FAPI_DBG("%s dqs_align_cycles: %llu(%lluns)", mss::c_str(i_target), l_dqs_align_cycles, mss::cycles_to_ns(i_target,
-             l_dqs_align_cycles));
+    FAPI_DBG("%s dqs_align_cycles: %llu(%lluns)", mss::c_str(i_target), l_dqs_align_cycles,
+             mss::cycles_to_ns(i_target,
+                               l_dqs_align_cycles));
     return l_dqs_align_cycles;
 }
 

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -39,7 +39,7 @@
 #include <fapi2.H>
 #include <p9_mc_scom_addresses.H>
 #include <generic/memory/lib/utils/scom.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <lib/eff_config/timing.H>
 
 namespace mss

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H
@@ -299,10 +299,12 @@ inline fapi2::ReturnCode encode ( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
     //used to hold result from vector pair lookup
     OT l_encoding = 0;
 
-    //Returns true if found, so need to negate for FAPI_TRY
     //Failing out if we don't find an encoding. All suported types should be encoded above
-    FAPI_TRY( !mss::find_value_from_key (i_map, i_attr, l_encoding),
-              "Couldn't find encoding for power thermal encode for value: %x target: %s", i_attr, mss::c_str(i_target));
+    FAPI_ASSERT( mss::find_value_from_key (i_map, i_attr, l_encoding),
+                 fapi2::MSS_POWER_THERMAL_ENCODE_ERROR()
+                 .set_ATTR(i_attr)
+                 .set_DIMM_TARGET(i_target),
+                 "Couldn't find encoding for power thermal encode for value: %x target: %s", i_attr, mss::c_str(i_target));
     o_buf.insertFromRight<S, L>(l_encoding);
 
 fapi_try_exit:
@@ -330,9 +332,13 @@ inline fapi2::ReturnCode decode ( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&
     //used to hold result from vector pair lookup
     OT l_encoding = 0;
     i_buf.extractToRight<S, L>(l_encoding);
-    //Find_key_from_value returns fapi2 error
-    FAPI_TRY( mss::find_key_from_value (i_map, l_encoding, o_attr),
-              "Couldn't find encoding for power thermal decode for target: %s", mss::c_str(i_target));
+
+    //Failing out if we don't find an decoding. All suported types should be encoded above
+    FAPI_ASSERT( mss::find_key_from_value (i_map, l_encoding, o_attr),
+                 fapi2::MSS_POWER_THERMAL_DECODE_ERROR()
+                 .set_ATTR(l_encoding)
+                 .set_DIMM_TARGET(i_target),
+                 "Couldn't find encoding for power thermal decode for target: %s", mss::c_str(i_target));
 fapi_try_exit:
     return fapi2::current_err;
 }

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -120,15 +120,6 @@ enum sizes
 
 enum times
 {
-    DELAY_1NS               = 1,
-    DELAY_10NS              = 10 ,      ///< general purpose 10  ns delay for HW mode
-    DELAY_100NS             = 100,      ///< general purpose 100 ns delay for HW mode
-    DELAY_1US               = 1000,     ///< general purpose 1 usec delay for HW mode
-    DELAY_10US              = 10000,    ///< general purpose 1 usec delay for HW mode
-    DELAY_100US             = 100000,   ///< general purpose 100 usec delay for HW mode
-    DELAY_1MS               = 1000000,  ///< general purpose 1 ms delay for HW mode
-
-    // Not *exactly* a time but go with it.
     BG_SCRUB_IN_HOURS       = 12,
 
     CMD_TIMEBASE            = 8192,     ///< Represents the timebase multiplier for the MCBIST inter cmd gap

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C
@@ -51,9 +51,10 @@
 #include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H>
 #include <generic/memory/lib/spd/spd_checker.H>
 #include <generic/memory/lib/spd/spd_utils.H>
-#include <lib/utils/conversions.H>
+#include <lib/utils/mss_nimbus_conversions.H>
 #include <generic/memory/lib/utils/find.H>
 #include <lib/eff_config/timing.H>
+#include <lib/shared/mss_const.H>
 
 using fapi2::TARGET_TYPE_MCA;
 using fapi2::TARGET_TYPE_MCS;