PRD: Add regs to capture list for NVLINK analysis

Change-Id: I5be61c2a841b132bbca4a09a8466feb1130efc97 CQ:SW416893 Backport: release-op910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54717 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54783 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
open-power · Mar 1, 2018 · 2993c5b · 2993c5b
1 parent 0c2ad40
commit 2993c5b
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Showing 5 changed files with 116 additions and 2 deletions.
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule b/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule
@@ -6807,7 +6807,7 @@ group gNPU0FIR filter singlebit, cs_root_cause( 1, 2, 3, 4, 5, 6, 7, 9, 10, 16,
     /** NPU0FIR[19]
      *  CQ CTL/SM NVF NVLink fatal error
      */
-    (rNPU0FIR, bit(19)) ? self_th_1;
+    (rNPU0FIR, bit(19)) ? nvLinkAssist;
 
     /** NPU0FIR[20]
      *  spare

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
@@ -6787,7 +6787,7 @@ group gNPU0FIR filter singlebit, cs_root_cause( 1, 2, 3, 4, 5, 6, 7, 9, 10, 16,
     /** NPU0FIR[19]
      *  CQ CTL/SM NVF NVLink fatal error
      */
-    (rNPU0FIR, bit(19)) ? self_th_1;
+    (rNPU0FIR, bit(19)) ? nvLinkAssist;
 
     /** NPU0FIR[20]
      *  spare

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule
@@ -114,3 +114,13 @@ actionclass pmRecovery
     funccall("PmRecovery");
     threshold1;
 };
+
+/** Used for NVLINK errors (open power)
+ *  which can be the cause of OPAL TIs
+ */
+actionclass nvLinkAssist
+{
+    capture(nvLinkErr);
+    self_th_1;
+};
+
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule
@@ -324,3 +324,92 @@
         capture     group default;
     };
 
+    ############################################################################
+    # NPU CERR for NVLINK (open power systems)
+    ############################################################################
+
+    register NPU_0_0_CERR
+    {
+        name        "NPU.STCK0.SM0.CERR";
+        scomaddr    0x05011017;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_0_1_CERR
+    {
+        name        "NPU.STCK0.SM1.CERR";
+        scomaddr    0x05011047;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_0_2_CERR
+    {
+        name        "NPU.STCK0.SM2.CERR";
+        scomaddr    0x05011077;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_0_3_CERR
+    {
+        name        "NPU.STCK0.SM3.CERR";
+        scomaddr    0x050110A7;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_1_0_CERR
+    {
+        name        "NPU.STCK1.SM0.CERR";
+        scomaddr    0x05011217;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_1_1_CERR
+    {
+        name        "NPU.STCK1.SM1.CERR";
+        scomaddr    0x05011247;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_1_2_CERR
+    {
+        name        "NPU.STCK1.SM2.CERR";
+        scomaddr    0x05011277;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_1_3_CERR
+    {
+        name        "NPU.STCK1.SM3.CERR";
+        scomaddr    0x050112A7;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_2_0_CERR
+    {
+        name        "NPU.STCK2.SM0.CERR";
+        scomaddr    0x05011417;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_2_1_CERR
+    {
+        name        "NPU.STCK2.SM1.CERR";
+        scomaddr    0x05011447;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_2_2_CERR
+    {
+        name        "NPU.STCK2.SM2.CERR";
+        scomaddr    0x05011477;
+        capture     group nvLinkErr;
+    };
+
+    register NPU_2_3_CERR
+    {
+        name        "NPU.STCK2.SM3.CERR";
+        scomaddr    0x050114A7;
+        capture     group nvLinkErr;
+    };
+
+
diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
@@ -309,6 +309,21 @@ void getAddresses( TrgtMap_t & io_targMap )
         0x04040018, // N2_CHIPLET_UCS_FIR
         0x04040019, // N2_CHIPLET_UCS_FIR_MASK
 
+        0x05011017, // NPU_STCK0_SM0_CERR
+        0x05011047, // NPU_STCK0_SM1_CERR
+        0x05011077, // NPU_STCK0_SM2_CERR
+        0x050110A7, // NPU_STCK0_SM3_CERR
+
+        0x05011217, // NPU_STCK1_SM0_CERR
+        0x05011247, // NPU_STCK1_SM1_CERR
+        0x05011277, // NPU_STCK1_SM2_CERR
+        0x050112A7, // NPU_STCK1_SM3_CERR
+
+        0x05011417, // NPU_STCK2_SM0_CERR
+        0x05011447, // NPU_STCK2_SM1_CERR
+        0x05011477, // NPU_STCK2_SM2_CERR
+        0x050114A7, // NPU_STCK2_SM3_CERR
+
         0x05040000, // N3_CHIPLET_CS_FIR
         0x05040001, // N3_CHIPLET_RE_FIR
         0x05040002, // N3_CHIPLET_FIR_MASK