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WR_LVL Termination Fix (Qoff) for p9c, DDR4 only
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Change-Id: Iabc29772b0618231bee469b65bcbe30e76935486
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57201
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57208
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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stermole authored and dcrowell77 committed May 16, 2018
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236 changes: 236 additions & 0 deletions src/import/chips/centaur/procedures/hwp/memory/lib/shared/delayRegs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -22,3 +22,239 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file delayRegs.H
/// @brief Const arrays for delay registers, indexed by port, rank, dp18 block
///
/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 3
/// *HWP Consumed by: HB:CI
//
#ifndef DELAYREGS_H_
#define DELAYREGS_H_

constexpr uint64_t const l_disable_reg[MAX_PORTS_PER_MBA][NUM_RANK_GROUPS][MAX_BLOCKS_PER_RANK] =
{
/* port 0 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4
},
// primary rank pair 1
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4
}
},
/* port 1 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4
},
// primary rank p1
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3,
CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4
}
}
};

constexpr uint64_t const l_dqs_gate_delay[MAX_PORTS_PER_MBA][NUM_RANK_GROUPS][MAX_BLOCKS_PER_RANK] =
{
/* port 0 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4
},
// primary rank pair 1
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4
}
},
/* port 1 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4
},
// primary rank p1
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4
}
}
};

constexpr uint64_t const l_dqs_rd_phase_select[MAX_PORTS_PER_MBA][NUM_RANK_GROUPS][MAX_BLOCKS_PER_RANK] =
{
/* port 0 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4
},
// primary rank pair 1
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4
}
},
/* port 1 */
{
// primary rank pair 0
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4
},
// primary rank p1
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4
},
// primary rank pair 2
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4
},
// primary rank pair 3
{
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3,
CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4
}
}
};

#endif
6 changes: 3 additions & 3 deletions src/import/chips/centaur/procedures/hwp/memory/lib/shared/dimmConsts.H
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Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@
/// @file dimmConsts.H
/// @brief DIMM Constants
///
/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
/// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
/// *HWP Consumed by: HB:CI
Expand All @@ -45,6 +45,7 @@ enum consts : size_t
MAX_RANKS_PER_DIMM = 4, ///< Maximum number of ranks on a DIMM
NUM_RANK_GROUPS = 4, ///< Maximum number of rank groups
MAX_RANKS_PER_PORT = 8, ///< Maximum number of ranks on a port
MAX_RANKS_PER_RANK_GROUP = 4, ///< Maximum number of ranks in a rank group
DIMM_DQ_RANK_BITMAP_SIZE = 10, ///< Size in bytes of the Bad DQ bitmap for a rank.

BITS_PER_BYTE = 8,
Expand Down Expand Up @@ -169,5 +170,4 @@ enum sim_cycles : size_t
DELAY_2000000SIMCYCLES = 2000000, ///< 2000000 sim cycle delay for sim mode (100 usec if simclk = 20Ghz)
DELAY_10000000SIMCYCLES = 10000000, ///< 10000000 sim cycle delay for sim mode
};

#endif

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