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PM: Addressed TODOs in hcode image build HWP.
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Commit addresses TODOs which were found to be functional.
Code has been updated for those which needed an investigation.
TODOs which intend design improvement has been deferred for next
release.

Change-Id: I68eb6c388cc9ff6bb72b79d9de718baa2812beab
RTC: 184604
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59317
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59347
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@premsjha @dcrowell77
premsjha authored and dcrowell77 committed May 28, 2018
1 parent ccc4804 commit 2b37fd2
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Showing 3 changed files with 34 additions and 21 deletions.
17 changes: 6 additions & 11 deletions src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,6 @@ namespace p9_hcodeImageBuild
#endif //__cplusplus
#endif //__ASSEMBLER__

//FIXME to make future addition simple, need a better solution
/**
* @brief returns maximum quad common rings that enter HOMER.
*/
Expand Down Expand Up @@ -255,9 +254,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
#ifdef __ASSEMBLER__
.endm
#else
//FIXME RTC 155018
//Eventually SGPE Img header has been defined to be of size 96B. Next 36B would be for
//debug pointer.Aligning SGPE image header to 64B boundary.
//SGPE header size is 96B
} __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) sgpeHeader_t;
#endif

Expand Down Expand Up @@ -299,9 +296,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
#ifdef __ASSEMBLER__
.endm
#else
//FIXME RTC 155018
//Eventually CME Img header might be of size 96B. Next 36B would be for
//debug pointer.Aligning CME image header to 64B boundary.
//CME Header size is 96B
} __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) cmeHeader_t;
#endif

Expand Down Expand Up @@ -364,9 +359,7 @@ HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional
#ifdef __ASSEMBLER__
.endm
#else
//FIXME RTC 155018
//Eventually PGPE Img header has been defined to be of size 96B. Next 36B would be for
//debug pointer.Aligning PGPE image header to 64B boundary.
//PGPE Header size is 128B
} __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) PgpeHeader_t;
#endif

Expand Down Expand Up @@ -618,6 +611,7 @@ typedef struct
uint8_t cmeSramRegion[CME_REGION_SIZE];
} CPMRLayout_t;


/**
* @brief models image section associated with PGPE in HOMER.
*/
Expand All @@ -631,7 +625,8 @@ typedef struct
uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE];
uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB
uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)];
uint8_t pstateTable[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE]; // PPMR + 144KB
uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB
uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)];
uint8_t ppmr_reserved1[WOF_TABLE_RESERVE];
uint8_t wofTableSize[OCC_WOF_TABLES_SIZE]; //WOF Tables located ar PPMR base + 768KB
} PPMRLayout_t;
Expand Down
21 changes: 13 additions & 8 deletions src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
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Original file line number Diff line number Diff line change
Expand Up @@ -1273,12 +1273,12 @@ void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState )
pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0);

FAPI_INF("CPMR SR");
FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus,
SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags));
FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)",
FAPI_INF("Fuse Mode : 0x%08X", pCpmrHdr->fusedModeStatus );
FAPI_INF("CME Image Flag : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags));
FAPI_DBG("CME Image Offset : 0x%08X, Header value 0x%08X (Real offset / 32)",
SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32,
SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
FAPI_DBG("CME Image Size : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));

FAPI_INF("<< updateCpmrHeaderSR");
}
Expand Down Expand Up @@ -1519,8 +1519,8 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn,
{

FAPI_INF(">> buildCoreRestoreImage");
uint32_t rcTemp = IMG_BUILD_SUCCESS;
fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
uint32_t rcTemp = IMG_BUILD_SUCCESS;
fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
//Let us find XIP Header for Core Self Restore Image
P9XipSection ppeSection;
uint8_t* pSelfRestImg = NULL;
Expand Down Expand Up @@ -1580,7 +1580,6 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn,
.set_ACTUAL_SIZE( ppeSection.iv_size ),
"Failed to update CPMR Header in HOMER" );


if( i_imgType.coreSprBuild )
{
//Pad undefined or runtime section with ATTN Opcode
Expand Down Expand Up @@ -1838,7 +1837,13 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip
i_procFuncModel.getChipLevel(),
ppeSection );

//FIXME RTC 178555 Add size check for PGPE Auxiliary Task binary.
FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rcTemp ),
fapi2::P9_PGPE_AUX_TASK_BIN_SIZE_ERROR()
.set_EC_LEVEL( i_procFuncModel.getChipLevel() )
.set_CHIP_TYPE( i_procFuncModel.getChipName() )
.set_MAX_ALLOWED_SIZE( rcTemp )
.set_ACTUAL_SIZE( ppeSection.iv_size ),
"Failed to copy PGPE Aux Task Binary due to bad size" );

io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_hcode_offset + PGPE_IMAGE_SIZE;
io_ppmrHdr.g_ppmr_aux_task_length = ppeSection.iv_size;
Expand Down
17 changes: 15 additions & 2 deletions src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand Down Expand Up @@ -688,5 +688,18 @@
</hwpError>

<!-- *********************************************************************** -->

<hwpError>
<rc>RC_P9_PGPE_AUX_TASK_BIN_SIZE_ERROR</rc>
<description>hcode image build procedure failed to build PPMR region due to a bad
size of auxiliary task binary </description>
<ffdc>EC_LEVEL</ffdc>
<ffdc>CHIP_TYPE</ffdc>
<ffdc>MAX_ALLOWED_SIZE</ffdc>
<ffdc>ACTUAL_SIZE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
</hwpErrors>

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