Register Scom Device Routes for OMI, OMIC , and MCC targets

While adding in support for OCMB scoms I noticed that we were
missing some plumbing for the new chiplets in P9A. Looks like the
P9N/P9C chiplets were registered when scomtrans.C was orginally
written back in the genesis of P9. This is why we probably missed
updating this when adding Axone targets. Also this commit updates
getChipLevel function to find Axone EC levels correctly. Right
now supported Axone EC is 0x10 and 0x20 for DD1 and a preemptive
DD2 support also.

Change-Id: I49de46e1f8774f7e418d8c4f94c72a14d84a0e6d
RTC:196806
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

src/usr/scom/scomtrans.C

@@ -172,6 +172,21 @@ DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
                         TARGETING::TYPE_CAPP,
                         startScomProcess);
 
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+                      DeviceFW::SCOM,
+                      TARGETING::TYPE_MCC,
+                      startScomProcess);
+
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+                      DeviceFW::SCOM,
+                      TARGETING::TYPE_OMIC,
+                      startScomProcess);
+
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+                      DeviceFW::SCOM,
+                      TARGETING::TYPE_OMI,
+                      startScomProcess);
+
 //////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////
 errlHndl_t startScomProcess(DeviceFW::OperationType i_opType,
@@ -1039,6 +1054,25 @@ uint32_t getChipLevel (TARGETING::Target* i_target)
                     assert(false,"Unsupported Cumulus EC");
             }
             break;
+        case(TARGETING::MODEL_AXONE):
+            switch(l_ec)
+            {
+                case(0x10):
+                    l_chipLevel = P9A_DD1_SI_MODE;
+                    break;
+                case(0x20):
+                    l_chipLevel = P9A_DD2_SI_MODE;
+                    break;
+                case(0x00):
+                    // before ATTR_EC is set, default to newest level that exists
+                    l_chipLevel = P9A_DD1_SI_MODE;
+                    break;
+                default:
+                    TRACFCOMP( g_trac_scom,
+                               "Unsupported Axone EC 0x%X", l_ec );
+                    assert(false,"Unsupported Axone EC");
+            }
+            break;
         default:
             TRACFCOMP( g_trac_scom,
                        "Unsupported Chip Type %d", l_model );