Add MSS customization support from CRP0 Lx MVPD

  Keyword V0 offsets are the same as V1
  Move bad-bits error processing to 1.03

Change-Id: I233b3142ea8e8b08621b88a4b3af5417bbde5745
Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58313

src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk

@@ -50,6 +50,7 @@ $(WRAPPER)_DEPLIBS+=p9_mss_freq_drift
 $(WRAPPER)_DEPLIBS+=p9_mss_scominit
 $(WRAPPER)_DEPLIBS+=p9_mss_thermal_init
 $(WRAPPER)_DEPLIBS+=p9_mss_throttle_mem
+$(WRAPPER)_DEPLIBS+=p9_mss_attr_update
 
 # USELIBS to get the header, DEPLIBS to get the so
 $(WRAPPER)_USELIBS+=p9_getecid