PCIe updates for Nimbus DD2 GEN4 operation

adjust REFISRC, REFISINK, VBGENDOC in PCIE PLL inits for all ECs set EDMOD in RX VGA Control Register 1 for DD2 only Change-Id: Ib10b02fb49dbf7ccf8dcad2ada5ac463a927d4c7 CQ: HW414759 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42423 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Ricardo Mata <ricmata@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42431 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
open-power · Jul 10, 2017 · 3793f8b · 3793f8b
1 parent 09611ce
commit 3793f8b
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Showing 3 changed files with 39 additions and 4 deletions.
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -60,6 +60,10 @@ REG64_FLD(PU_TX_CH_MISC_WEN0,                    12, SH_UNT, SH_ACS_SCOM, SH_FLD
 REG64_FLD(PU_TX_CH_MISC_WEN1,                    13, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
 REG64_FLD(PU_TX_CH_MISC_WEN2,                    14, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
 
+// RX VGA Control Register1
+REG64_FLD(PEC_SCOM0X0B_EDMOD,                    52, SH_UNT_PEC, SH_ACS_SCOM, SH_FLD_UNUSED);
+REG64_FLD(PEC_SCOM0X0B_EDMOD_LEN,                 2, SH_UNT_PEC, SH_ACS_SCOM, SH_FLD_UNUSED);
+
 //Example
 //Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
 //and add another paramter that is the new value you want.

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
@@ -125,10 +125,14 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
     uint8_t l_attr_8 = 0;
     uint16_t l_attr_16 = 0;
     uint32_t l_poll_counter; //Number of iterations while polling for PLLA and PLLB Port Ready Status
+    uint8_t l_hw414759 = 0;
 
     FAPI_DBG("target vec size: %#x", l_pec_chiplets_vec.size());
     FAPI_DBG("l_buf: %#x", l_buf());
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414759, i_target, l_hw414759),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW414759)");
+
     for (auto l_pec_chiplets : l_pec_chiplets_vec)
     {
         // Get the pec id
@@ -348,9 +352,18 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
                                        56, 7);
 
         // Phase1 init step 20 (RX VGA Control Register 1)
-        SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1,
-                                       PEC_PCS_RX_VGA_CONTROL1_REG,
-                                       48, 16);
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1,
+                               l_pec_chiplets,
+                               l_attr_16));
+        FAPI_TRY(l_buf.insertFromRight(l_attr_16, 48, 16));
+
+        if (l_hw414759)
+        {
+            l_buf.setBit<PEC_SCOM0X0B_EDMOD, PEC_SCOM0X0B_EDMOD_LEN>();
+        }
+
+        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_VGA_CONTROL1_REG, l_buf));
 
         // Phase1 init step 21 (RX VGA Control Register 2)
         SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG2,

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -3262,6 +3262,24 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW414759</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD2.0 only -- apply PCI PLL and VGA gain EDGEMOD workarounds
+      to enable GEN4 operation
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->
   <!-- ******************************************************************** -->