add support for OBUS PLL buckets

p9_frequency_buckets.H
p9.obus.pll.scan.initfile
  document and support base frequencies
    1611 MHz - 25.78G, 156.25 MHz ref
    1250 MHz - 25G, 156.25 MHz ref
    1200 MHz - 19.2G, 133.33 MHz ref

pervasive_attributes.xml
  define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value

nest_attributes.xml
  define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency
  retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit bucket selection through FSP/BMC->SBE mailbox
  encode OBUS bucket selects in Scratch Reg2 bits 24:31

p9_sbe_chiplet_pll_initf.C
p9_sbe_chiplet_pll_initf_errors.xml
  scan correct ring image based on bucket selector attributes

p9_ringId.C
p9_ringId.H
p9_ring_id.h
  accomodate three copies of obX_pll_bndy (use ID previously reserved for
  obX_pll_func, which should not be necessary to scan init)

scan_procedures.mk
generateWrapper.pl
  initCompiler infrastructure changes to support build of bucket data

p9.fbc.ab_hp.scom.initfile
p9.fbc.ioo_tl.scom.initfile
p9_tod_setup.C
  updates to handle A,O frequency attribute changes

Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40165
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/common/include/p9_frequency_buckets.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -64,3 +64,16 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
     2666,
     2666
 };
+
+// constant definining number of OBUS PLL frequency options ('buckets')
+// to be built into unsigned HW image
+const uint8_t OBUS_PLL_FREQ_BUCKETS = 3;
+
+// OBUS PLL frequency in MHz
+// index is bucket number
+const uint32_t OBUS_PLL_FREQ_LIST[OBUS_PLL_FREQ_BUCKETS] =
+{
+    1611,
+    1250,
+    1200
+};

src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_tl_scom.C

@@ -81,18 +81,25 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                                             || (l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_1] != literal_0));
         uint64_t l_def_OBUS0_FBC_ENABLED = ((l_TGT0_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG[literal_3] != literal_0)
                                             || (l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_0] != literal_0));
-        fapi2::ATTR_FREQ_A_MHZ_Type l_TGT1_ATTR_FREQ_A_MHZ;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, TGT1, l_TGT1_ATTR_FREQ_A_MHZ));
+        fapi2::ATTR_FREQ_O_MHZ_Type l_TGT0_ATTR_FREQ_O_MHZ;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_O_MHZ, TGT0, l_TGT0_ATTR_FREQ_O_MHZ));
         fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT1_ATTR_FREQ_PB_MHZ;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, TGT1, l_TGT1_ATTR_FREQ_PB_MHZ));
-        uint64_t l_def_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT1_ATTR_FREQ_A_MHZ * literal_12));
-        uint64_t l_def_OBUS0_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS0_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_0] *
+                                           literal_12));
+        uint64_t l_def_OBUS0_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_0] * literal_10);
         uint64_t l_def_OBUS0_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_154);
-        uint64_t l_def_OBUS1_LO_LIMIT_D = l_TGT1_ATTR_FREQ_A_MHZ;
+        uint64_t l_def_OBUS1_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_1] *
+                                           literal_12));
+        uint64_t l_def_OBUS1_LO_LIMIT_D = l_TGT0_ATTR_FREQ_O_MHZ[literal_1];
         uint64_t l_def_OBUS1_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_12);
-        uint64_t l_def_OBUS2_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS2_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_2] *
+                                           literal_12));
+        uint64_t l_def_OBUS2_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_2] * literal_10);
         uint64_t l_def_OBUS2_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_74);
-        uint64_t l_def_OBUS3_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS3_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_3] *
+                                           literal_12));
+        uint64_t l_def_OBUS3_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_3] * literal_10);
         uint64_t l_def_OBUS3_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_95);
         fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE_Type l_TGT1_ATTR_PROC_FABRIC_SMP_OPTICS_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_SMP_OPTICS_MODE));
@@ -129,7 +136,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS0_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS0_FBC_ENABLED && (l_def_OBUS0_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x36 - (l_def_OBUS0_LO_LIMIT_N / l_def_OBUS0_LO_LIMIT_D)) );
             }
@@ -143,7 +150,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS0_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS0_FBC_ENABLED && (l_def_OBUS0_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x36 - (l_def_OBUS0_LO_LIMIT_N / l_def_OBUS0_LO_LIMIT_D)) );
             }
@@ -167,7 +174,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS1_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS1_FBC_ENABLED && (l_def_OBUS1_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x2A - (l_def_OBUS1_LO_LIMIT_N / l_def_OBUS1_LO_LIMIT_D)) );
             }
@@ -181,7 +188,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS1_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS1_FBC_ENABLED && (l_def_OBUS1_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x2A - (l_def_OBUS1_LO_LIMIT_N / l_def_OBUS1_LO_LIMIT_D)) );
             }
@@ -205,7 +212,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS2_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS2_FBC_ENABLED && (l_def_OBUS2_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x1B - (l_def_OBUS2_LO_LIMIT_N / l_def_OBUS2_LO_LIMIT_D)) );
             }
@@ -219,7 +226,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS2_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS2_FBC_ENABLED && (l_def_OBUS2_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x1B - (l_def_OBUS2_LO_LIMIT_N / l_def_OBUS2_LO_LIMIT_D)) );
             }
@@ -243,7 +250,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS3_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS3_FBC_ENABLED && (l_def_OBUS3_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x22 - (l_def_OBUS3_LO_LIMIT_N / l_def_OBUS3_LO_LIMIT_D)) );
             }
@@ -257,7 +264,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS3_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS3_FBC_ENABLED && (l_def_OBUS3_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x22 - (l_def_OBUS3_LO_LIMIT_N / l_def_OBUS3_LO_LIMIT_D)) );
             }

src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H

@@ -27389,8 +27389,8 @@ fapi_try_exit:
 /// @param[out] uint32_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  The frequency of a processor's A link clocks, in MHz. This is the same for all
-/// chips in the system. Provided by the
+/// @note  The frequency of a processor's Abus, in MHz. This is the same for all chips in
+/// the system. Provided by the
 /// MRW.
 ///
 inline fapi2::ReturnCode freq_a_mhz(uint32_t& o_value)
@@ -27410,8 +27410,8 @@ fapi_try_exit:
 /// @param[out] uint32_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  The frequency of a processor's X link clocks, in MHz. This is the same for all
-/// chips in the system. Provided by the
+/// @note  The frequency of a processor's Xbus mesh clocks, in MHz. This is the same for
+/// all chips in the system. Provided by the
 /// MRW.
 ///
 inline fapi2::ReturnCode freq_x_mhz(uint32_t& o_value)

src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C

@@ -1050,14 +1050,14 @@ fapi_try_exit:
 /// @brief Calculates the delay for a node in TOD-grid-cycles
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x XBUS frequency in MHz
-/// @param[in] i_freq_o OBUS frequency in MHz
+/// @param[in] i_freq_a OBUS frequency in MHz
 /// @param[out] o_node_delay => Delay of a single node in TOD-grid-cycles
 /// @return FAPI_RC_SUCCESS if TOD node delay is successfully calculated else
 ///         error
 fapi2::ReturnCode calculate_node_link_delay(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     uint32_t& o_node_delay)
 {
     fapi2::buffer<uint64_t> l_rt_delay_ctl_reg = 0;
@@ -1151,7 +1151,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS0),
                         "i_tod_node->i_bus_rx is set to OBUS0 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_0>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_1>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1168,7 +1168,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS1),
                         "i_tod_node->i_bus_rx is set to OBUS1 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_2>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_3>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1185,7 +1185,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS2),
                         "i_tod_node->i_bus_rx is set to OBUS2 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_4>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_5>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1202,7 +1202,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS3),
                         "i_tod_node->i_bus_rx is set to OBUS3 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_6>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_7>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1275,14 +1275,14 @@ fapi_try_exit:
 ///        node delay)
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x XBUS frequency in MHz
-/// @param[in] i_freq_o OBUS frequency in MHz
+/// @param[in] i_freq_a OBUS frequency in MHz
 /// @param[out] o_longest_delay Longest delay in TOD-grid-cycles
 /// @return FAPI_RC_SUCCESS if a longest TOD delay was found in topology
 ///         else error
 fapi2::ReturnCode calculate_longest_topolopy_delay(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     uint32_t& o_longest_delay)
 {
     uint32_t l_node_delay = 0;
@@ -1292,7 +1292,7 @@ fapi2::ReturnCode calculate_longest_topolopy_delay(
 
     FAPI_TRY(calculate_node_link_delay(i_tod_node,
                                        i_freq_x,
-                                       i_freq_o,
+                                       i_freq_a,
                                        l_node_delay),
              "Error from calculate_node_link_delay!");
     o_longest_delay = l_node_delay;
@@ -1304,7 +1304,7 @@ fapi2::ReturnCode calculate_longest_topolopy_delay(
         tod_topology_node* l_tod_node = *l_child;
         FAPI_TRY(calculate_longest_topolopy_delay(l_tod_node,
                  i_freq_x,
-                 i_freq_o,
+                 i_freq_a,
                  l_node_delay),
                  "Error from calculate_longest_topology_delay!");
 
@@ -1325,14 +1325,14 @@ fapi_try_exit:
 /// @brief Updates the topology struct with the final delay values
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x  XBUS frequency in MHz
-/// @param[in] i_freq_o  OBUS frequency in MHz
+/// @param[in] i_freq_a  OBUS frequency in MHz
 /// @param[in] i_longest_delay Longest delay in the topology
 /// @return FAPI_RC_SUCCESS if o_int_path_delay was set for every node in the
 ///         topology else error
 fapi2::ReturnCode set_topology_delays(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     const uint32_t i_longest_delay)
 {
     FAPI_DBG("Start");
@@ -1350,7 +1350,7 @@ fapi2::ReturnCode set_topology_delays(
                 .set_PATH_DELAY(i_tod_node->o_int_path_delay)
                 .set_LONGEST_DELAY(i_longest_delay)
                 .set_XBUS_FREQ(i_freq_x)
-                .set_OBUS_FREQ(i_freq_o),
+                .set_OBUS_FREQ(i_freq_a),
                 "Invalid delay of %d calculated!");
 
     // Recurse on downstream nodes
@@ -1360,7 +1360,7 @@ fapi2::ReturnCode set_topology_delays(
     {
         FAPI_TRY(set_topology_delays(*l_child,
                                      i_freq_x,
-                                     i_freq_o,
+                                     i_freq_a,
                                      i_tod_node->o_int_path_delay),
                  "Error from set_topology_delays!");
     }
@@ -1380,33 +1380,33 @@ fapi2::ReturnCode calculate_node_delays(tod_topology_node* i_tod_node)
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     uint32_t l_longest_delay = 0;
     uint32_t l_freq_x = 0;
-    uint32_t l_freq_o = 0;
+    uint32_t l_freq_a = 0;
 
     FAPI_DBG("Start");
     // retrieve X-bus and A-bus frequencies
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_X_MHZ, FAPI_SYSTEM, l_freq_x),
              "Failure reading XBUS frequency attribute!");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, FAPI_SYSTEM, l_freq_o),
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, FAPI_SYSTEM, l_freq_a),
              "Failure reading OBUS frequency attribute!");
 
     // multiply attribute (mesh speed) speed by link factor
     l_freq_x *= 8;
-    l_freq_o *= 16;
+    l_freq_a *= 16;
 
     // Bus frequencies are global for the system (i.e. A0 and A1 will always
     //  run with the same frequency)
-    FAPI_DBG("XBUS=%dMHz OBUS=%dMHz", l_freq_x, l_freq_o);
+    FAPI_DBG("XBUS=%dMHz OBUS=%dMHz", l_freq_x, l_freq_a);
 
     // Find the most-delayed path in the topology; this is the MDMT's delay
     FAPI_TRY(calculate_longest_topolopy_delay(i_tod_node,
              l_freq_x,
-             l_freq_o,
+             l_freq_a,
              l_longest_delay),
              "Error from calculate_longest_topology_delay!");
     FAPI_DBG("The longest delay is %d TOD-grid-cycles.", l_longest_delay);
     FAPI_TRY(set_topology_delays(i_tod_node,
                                  l_freq_x,
-                                 l_freq_o,
+                                 l_freq_a,
                                  l_longest_delay),
              "Error from set_topology_delays!");
 

src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C

@@ -58,6 +58,14 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT  = 17,
     ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT  = 18,
     ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT  = 19,
+    ATTR_OB0_PLL_BUCKET_STARTBIT       = 24,
+    ATTR_OB0_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB1_PLL_BUCKET_STARTBIT       = 26,
+    ATTR_OB1_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB2_PLL_BUCKET_STARTBIT       = 28,
+    ATTR_OB2_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB3_PLL_BUCKET_STARTBIT       = 30,
+    ATTR_OB3_PLL_BUCKET_LENGTH         = 2,
 
     // Scratch_reg_3
     ATTR_BOOT_FLAGS_STARTBIT           = 0,
@@ -66,14 +74,14 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     // Scratch_reg_4
     ATTR_BOOT_FREQ_MULT_STARTBIT       = 0,
     ATTR_BOOT_FREQ_MULT_LENGTH         = 16,
-    ATTR_NEST_PLL_BUCKET_STARTBIT      = 24,
-    ATTR_NEST_PLL_BUCKET_LENGTH        = 8,
     ATTR_CP_FILTER_BYPASS_BIT          = 16,
     ATTR_SS_FILTER_BYPASS_BIT          = 17,
     ATTR_IO_FILTER_BYPASS_BIT          = 18,
     ATTR_DPLL_BYPASS_BIT               = 19,
     ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT   = 20,
     ATTR_OBUS_RATIO_VALUE_BIT          = 21,
+    ATTR_NEST_PLL_BUCKET_STARTBIT      = 29,
+    ATTR_NEST_PLL_BUCKET_LENGTH        = 3,
 
     // Scratch_reg_5
     ATTR_PLL_MUX_STARTBIT              = 12,
@@ -147,6 +155,10 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch2_reg
     {
+        uint8_t l_ob0_pll_bucket;
+        uint8_t l_ob1_pll_bucket;
+        uint8_t l_ob2_pll_bucket;
+        uint8_t l_ob3_pll_bucket;
 
         FAPI_DBG("Reading Scratch_reg2");
         //Getting SCRATCH_REGISTER_2 register value
@@ -195,6 +207,17 @@ fapi2::ReturnCode p9_setup_sbe_config(const
             }
         }
 
+        FAPI_DBG("Reading OB PLL buckets");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket));
+
+        l_read_scratch_reg.insertFromRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
+
         FAPI_DBG("Setting up value of Scratch_reg2");
         //Setting SCRATCH_REGISTER_2 register value
         //CFAM.SCRATCH_REGISTER_2 = l_read_scratch_reg
@@ -254,7 +277,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
 
         l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
-        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);
+        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1 & 0x7);
 
         l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
         l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);