Revert ATTR_CEN_ECID back to ATTR_ECID

Firmware needs a common attribute for all chip targets Change-Id: Ia448b73bed691f493c7edb98e675e6febce74d23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49941 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49945 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
open-power · Dec 1, 2017 · 453d38a · 453d38a
1 parent 716a165
commit 453d38a
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Showing 3 changed files with 3 additions and 18 deletions.
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C
@@ -125,7 +125,7 @@ extern "C" {
         ecid[0] = ecid_struct.io_ecid[0];
         ecid[1] = ecid_struct.io_ecid[1];
 
-        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_ECID, i_target,  ecid), "mss_get_cen_ecid: Could not set ATTR_ECID" );
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_ECID, i_target,  ecid), "mss_get_cen_ecid: Could not set ATTR_ECID" );
 
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_CENTAUR_EC_FEATURE_CHECK_L4_CACHE_ENABLE_UNKNOWN,
                                i_target, l_checkL4CacheEnableUnknown),

diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
@@ -2788,19 +2788,6 @@ bits6:7  will be consumed together to form COARSE_LVL. </description>
     <array> 2 4 4</array>
 </attribute>
 
-<attribute>
-    <id>ATTR_CEN_ECID</id>
-    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
-Created from running the mss_get_cen_ecid.C
-Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description>
-    <valueType>uint64</valueType>
-    <writeable/>
-    <odmVisable/>
-    <odmChangeable/>
-    <array> 2</array>
-</attribute>
-
 <attribute>
     <id>ATTR_CEN_MSS_ALLOW_SINGLE_PORT</id>
     <targetType>TARGET_TYPE_MBA</targetType>

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -271,11 +271,9 @@
 
 <attribute>
   <id>ATTR_ECID</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType>
   <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
-  Created from running the mss_get_cen_ecid.C
-  Firmware shares some code with the processor,
-  so the attribute is named so they can point at a target and have common function.</description>
+  Populated by HWP called during IPL.</description>
   <valueType>uint64</valueType>
   <writeable/>
   <odmVisable/>