Set SBE console enable based on Hostboot config var

ATTR_LPC_CONSOLE_CNFG will shadow CONFIG_CONSOLE on
the master proc, always disabled on the slave chips.

Change-Id: Idf7286f91455148856b57ff66450c97862b3506e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66798
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

src/usr/targeting/common/xmltohb/hb_customized_attrs.xml

@@ -704,6 +704,13 @@
         <persistency>volatile-zeroed</persistency>
     </attribute>
 
+    <!-- Make this writeable so we can choose the value based on our CONFIG -->
+    <attribute>
+       <id>ATTR_LPC_CONSOLE_CNFG</id>
+       <persistency>volatile-zeroed</persistency>
+       <writeable/>
+    </attribute>
+
     <!-- This is only enabled for Wafer Test -->
     <attribute>
         <id>ATTR_START_CBS_FIFO_RESET_SKIP</id>

src/usr/targeting/targetservicestart.C

@@ -478,8 +478,34 @@ static void initializeAttributes(TargetService& i_targetService,
             }
             TARG_INF( "Setting RISK_LEVEL=%d", l_riskLevel );
             l_pTopLevel->setAttr<ATTR_RISK_LEVEL>(l_riskLevel);
+
+            //Set the SBE Console enablement based on our console enablement
+            ATTR_LPC_CONSOLE_CNFG_type l_consoleOn = LPC_CONSOLE_CNFG_ENABLE;
+#ifdef CONFIG_CONSOLE
+            l_consoleOn = LPC_CONSOLE_CNFG_DISABLE;
+#endif
+            l_pMasterProcChip->setAttr<ATTR_LPC_CONSOLE_CNFG>(l_consoleOn);
+
+        }
+
+        // Loop around all processors
+        TargetHandleList l_allProcChips;
+        getAllChips(l_allProcChips, TYPE_PROC, false);
+        for(auto l_chip : l_allProcChips)
+        {
+            // value for master set above
+            if( l_chip == l_pMasterProcChip )
+            {
+                continue;
+            }
+
+            //Turn the SBE Console enablement off for all slave chips
+            ATTR_LPC_CONSOLE_CNFG_type l_consoleOff = LPC_CONSOLE_CNFG_DISABLE;
+            l_chip->setAttr<ATTR_LPC_CONSOLE_CNFG>(l_consoleOff);
         }
 
+
+        // Do some special memory-preserving work
         if(i_isMpipl)
         {
             l_pTopLevel->setAttr<ATTR_IS_MPIPL_HB>(1);