Base Core/Kernel Changes to Support the Axone Processor Chip

  - Add the new cpu type, update the pvr checks and other
    miscellaneous changes to support a new Axone proc chip type

Change-Id: Ie2541bf826bdff65f6f11b0f16839855d69eb4d6
RTC: 173001
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64260
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/include/arch/pvrformat.H

@@ -113,13 +113,13 @@ struct PVR_t
      */
     enum
     {
-        NIMBUS_DD1_MASK = 0x00FF2F0F,
-        IS_NIMBUS_DD1   = 0x004E0100,
+        NIMBUS_DD1_MASK  = 0x00FF2F0F,
+        IS_NIMBUS_DD1    = 0x004E0100,
         IS_NIMBUS_DD20   = 0x004E0200,
         IS_NIMBUS_DD21   = 0x004E0201,
 
         // Field: chipType
-        NIMBUS_CHIP = 0,
+        NIMBUS_CHIP  = 0,
         CUMULUS_CHIP = 1,
 
         // Field: smt
@@ -130,7 +130,8 @@ struct PVR_t
         P8_MURANO = 0x4B,
         P8_NAPLES = 0x4C,
         P8_VENICE = 0x4D,
-        P9_ALL    = 0x4E,
+        P9_ALL    = 0x4E, //NIMBUS/CUMULUS
+        P9_AXONE  = 0x4F,
     };
 
     /**

src/include/sys/misc.h

@@ -134,6 +134,8 @@ enum ProcessorCoreType
     CORE_POWER9_NIMBUS,
     /** Power9 "CUMULUS" (scale-up) core */
     CORE_POWER9_CUMULUS,
+    /** Power9' "AXONE" core */
+    CORE_POWER9_AXONE,
 
     CORE_UNKNOWN,
 };

src/kernel/basesegment.C

@@ -59,6 +59,7 @@ void BaseSegment::_init()
         case CORE_POWER8_NAPLES:
         case CORE_POWER9_NIMBUS:
         case CORE_POWER9_CUMULUS:
+        case CORE_POWER9_AXONE:
         default:
             iv_physMemSize = VMM_BASE_BLOCK_SIZE;
             break;

src/kernel/cpuid.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -67,6 +67,9 @@ namespace CpuID
                 }
             }
 
+            case PVR_t::P9_AXONE:
+               return CORE_POWER9_AXONE;
+
             default:
                 return CORE_UNKNOWN;
         }

src/kernel/cpumgr.C

@@ -469,6 +469,7 @@ size_t CpuManager::getThreadCount()
 
         case CORE_POWER9_NIMBUS:
         case CORE_POWER9_CUMULUS:
+        case CORE_POWER9_AXONE:
             threads = 4;
             break;
 

src/kernel/exception.C

@@ -301,6 +301,7 @@ void kernel_execute_softpatch()
             case CORE_POWER8_NAPLES:
             case CORE_POWER9_NIMBUS:
             case CORE_POWER9_CUMULUS:
+            case CORE_POWER9_AXONE:
             case CORE_UNKNOWN:
                 p8_softpatch_denorm_assist(t->fp_context);
                 break;

src/kernel/misc.C

@@ -510,6 +510,7 @@ namespace KernelMisc
             case CORE_POWER8_NAPLES:
             case CORE_POWER9_NIMBUS:
             case CORE_POWER9_CUMULUS:
+            case CORE_POWER9_AXONE:
                 startAddr = reinterpret_cast<uint64_t*>
                                          ( VmmManager::INITIAL_MEM_SIZE ) ;
                 endAddr = reinterpret_cast<uint64_t*>(i_expandSize);
@@ -574,6 +575,7 @@ namespace KernelMisc
               break;
           case CORE_POWER9_NIMBUS:
           case CORE_POWER9_CUMULUS:
+          case CORE_POWER9_AXONE:
           case CORE_UNKNOWN:
           default:
               // See EX07.EC.CC.PCC0.COMMON.SPR_COMMON.SCOMC in scomdef for
@@ -660,6 +662,7 @@ const char* ProcessorCoreTypeStrings[]
     "Naples",
     "Nimbus",
     "Cumulus",
+    "Axone",
     "Unknown"
 };
 

src/lib/syscall_misc.C

@@ -71,6 +71,7 @@ size_t cpu_thread_count()
             break;
         case CORE_POWER9_NIMBUS:
         case CORE_POWER9_CUMULUS:
+        case CORE_POWER9_AXONE:
             threads = 4;
             break;
 

src/lib/syscall_mmio.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2010,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2010,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -75,6 +75,7 @@ static uint64_t mmio_scratch_base()
             return 0x40;
         case CORE_POWER9_NIMBUS:
         case CORE_POWER9_CUMULUS:
+        case CORE_POWER9_AXONE:
         case CORE_UNKNOWN:
         default:
             // See misc.C - updateScratchReg() for more info on this

src/usr/targeting/targetservicestart.C

@@ -345,6 +345,12 @@ static void checkProcessorTargeting(TargetService& i_targetService)
                     l_haveOneCorrectProcessor = true;
                 }
                 break;
+            case MODEL_AXONE:
+                if(l_coreType == CORE_POWER9_AXONE)
+                {
+                    l_haveOneCorrectProcessor = true;
+                }
+                break;
 
             default:
                 break;