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p9_sbe_lpc_init: Fix timeout setup
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Factor LPC register access out into its own utility function, with
added timeout for the ADU access and proper FFDC if the ADU times out.

CQ: SW418354
Change-Id: Id08653f49ddb66442533bf93a7a2ce8f72135c11
Original-Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71481
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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@fenkes-ibm @crgeddes
fenkes-ibm authored and crgeddes committed Feb 12, 2019
1 parent 47b5923 commit 4f5f632
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Showing 2 changed files with 27 additions and 37 deletions.
57 changes: 21 additions & 36 deletions src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
///
/// @brief procedure to initialize LPC to enable communictation to PNOR
//------------------------------------------------------------------------------
// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Owner : Joachim Fenkes <fenkes@de.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
Expand All @@ -44,6 +44,9 @@
#include "p9_misc_scom_addresses.H"
#include "p9_misc_scom_addresses_fld.H"

const bool LPC_UTILS_TIMEOUT_FFDC = true;
#include "p9_lpc_utils.H"

static fapi2::ReturnCode reset_lpc_master(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
Expand Down Expand Up @@ -79,32 +82,20 @@ fapi_try_exit:
static fapi2::ReturnCode reset_lpc_bus_via_master(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
fapi2::buffer<uint64_t> l_data64;
fapi2::buffer<uint64_t> l_lpcm_opb_master_control_register_data(0);

//Write to the LPCM OPB Master Control Register (address x'C001 0008')
l_lpcm_opb_master_control_register_data.setBit<PU_LPC_CMD_REG_RNW>().insertFromRight<PU_LPC_CMD_REG_ADR, PU_LPC_CMD_REG_ADR_LEN>
(LPCM_OPB_MASTER_CONTROL_REG).insertFromRight<PU_LPC_CMD_REG_SIZE, PU_LPC_CMD_REG_SIZE_LEN>(0x4);
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
"Erro writing the LPC_CMD_REG to get the current reset value");
FAPI_TRY(fapi2::getScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error getting the reset value");
fapi2::buffer<uint32_t> l_control;

//Set register bit 23 lpc_lreset_oe to b'1' and set lpc_lreset_out to b'0' to drive a low reset
l_data64.setBit<LPC_LRESET_OE>().clearBit<LPC_LRESET_OUT>();
l_lpcm_opb_master_control_register_data.clearBit<PU_LPC_CMD_REG_RNW>();
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
"Error writing to the LPC_CMD_REG to set lpc_lreset_oe");
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error setting lpc_lreset_oe");
FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control),
"Error reading the OPB master control register");
l_control.setBit<LPC_LRESET_OE>().clearBit<LPC_LRESET_OUT>();
FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control), "Error asserting LPC reset");

//Give the bus some time to reset
fapi2::delay(LPC_LRESET_DELAY_NS, LPC_LRESET_DELAY_NS);

//Clear bit 23 lpc_lreset_oe to stop driving the low reset
l_data64.clearBit<LPC_LRESET_OE>();
l_lpcm_opb_master_control_register_data.clearBit<PU_LPC_CMD_REG_RNW>();
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
"Error writing to the LPC_CMD_REG to clear lpc_lreset_oe");
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error clearing lpc_lreset_oe");
l_control.clearBit<LPC_LRESET_OE>();
FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control), "Error deasserting LPC reset");

return fapi2::FAPI2_RC_SUCCESS;

Expand Down Expand Up @@ -140,15 +131,10 @@ fapi_try_exit:
return fapi2::current_err;
}


fapi2::ReturnCode p9_sbe_lpc_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
const uint64_t C_LPC_TIMEOUT_ADDR = 0x00400000C001202C;
const uint64_t C_LPC_TIMEOUT_DATA = 0x00000000FE000000;
const uint64_t C_OPB_TIMEOUT_ADDR = 0x00400000C0010040;
const uint64_t C_OPB_TIMEOUT_DATA = 0x00000000FFFFFFFE;
fapi2::buffer<uint64_t> l_data64;
fapi2::buffer<uint32_t> l_data32;
uint8_t l_use_gpio = 0;
uint8_t l_is_fsp = 0;
FAPI_DBG("p9_sbe_lpc_init: Entering ...");
Expand Down Expand Up @@ -180,16 +166,15 @@ fapi2::ReturnCode p9_sbe_lpc_init(
//--- STEP 3: Program settings in LPC Master and FPGA
//------------------------------------------------------------------------------------------

//Set up the LPC timeout settings
l_data64 = C_LPC_TIMEOUT_ADDR;
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_data64), "Error tring to set LPC timeout address");
l_data64 = C_LPC_TIMEOUT_DATA;
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error trying to set LPC timeout data");
//Set up the OPB timeout settings
l_data64 = C_OPB_TIMEOUT_ADDR;
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_data64), "Error trying to set OPB timeout address");
l_data64 = C_OPB_TIMEOUT_DATA;
FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error trying to set OPB timeout data");
// Set up the LPC timeout settings - OPB master first, in case the LPC HC hangs
FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_TIMEOUT_REG, LPCM_OPB_MASTER_TIMEOUT_VALUE),
"Error trying to set up the OPB master timeout");
FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_data32), "Error reading OPB master control register");
l_data32.setBit<LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE>();
FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_data32), "Error enabling OPB master timeout");

FAPI_TRY(lpc_write(i_target_chip, LPCM_LPC_MASTER_TIMEOUT_REG, LPCM_LPC_MASTER_TIMEOUT_VALUE),
"Error trying to set up the LPC host controller timeout");

FAPI_DBG("p9_sbe_lpc_init: Exiting ...");

Expand Down
7 changes: 6 additions & 1 deletion src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,12 @@ extern "C"
const uint64_t LPC_LRESET_OE = 23;
const uint64_t LPC_LRESET_OUT = 22;
const uint32_t LPC_LRESET_DELAY_NS = 200000;
const uint64_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008;
const uint32_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008;
const uint32_t LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE = 2;
const uint32_t LPCM_OPB_MASTER_TIMEOUT_REG = 0xC0010040;
const uint32_t LPCM_OPB_MASTER_TIMEOUT_VALUE = 0x01312D00; // 50ms at 1600MHz Nest / 400MHz OPB
const uint32_t LPCM_LPC_MASTER_TIMEOUT_REG = 0xC001202C;
const uint32_t LPCM_LPC_MASTER_TIMEOUT_VALUE = 0xFE000000;
const uint32_t CPLT_CONF1_TC_LP_RESET = 12;
fapi2::ReturnCode p9_sbe_lpc_init(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
Expand Down

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