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PM: clear Hcode error injection bit upon PM complex reset
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- Clearomh the bits lets STOPs and PStates be restarted during the reset.
  Injection has to be done after the subsystem is initialized.
- Clear the CSAR bits in p9_pm_corequad_init(init)
- Clear SGPE and PGPE error inject bits in OCC Flag2 (p9_pm_stop_gpe_init and
  p9_pm_pstate_gpe_init respectively

Key_Cronus_Test=PM_REGRESS

Change-Id: I93bfe8d4b0959a6a305722df1e2c518f3dfc08fc
CQ:SW429797
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60024
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60029
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@stillgs @dcrowell77
stillgs authored and dcrowell77 committed Jun 14, 2018
1 parent 5caa7eb commit 520c2aa
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Showing 3 changed files with 41 additions and 9 deletions.
16 changes: 16 additions & 0 deletions src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@
/// Clear CME flags and scratch registers as these will be setup
/// via CME booting during SGPE boot
/// Clear PPM Errors
/// Clear Hcode Error Injection enable bits
/// Restore PPM Error mask value from HWP attribute
/// }
/// }
Expand Down Expand Up @@ -92,6 +93,7 @@
#include <p9_ppe_defs.H>
#include <p9_resclk_defines.H>
#include <p9_pstates_cmeqm.h>
#include <p9_pm_hcd_flags.h>
#include <p9_pm_utils.H>

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -340,6 +342,20 @@ fapi2::ReturnCode pm_corequad_init(
FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64),
"ERROR: Failed to clear CORE PPM ERROR");

FAPI_INF("Clearing Hcode Error Injection and other CSAR settings ...");
// *INDENT-OFF*
l_data64.flush<0>()
.setBit<p9hcd::CPPM_CSAR_FIT_HCODE_ERROR_INJECT>()
.setBit<p9hcd::CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK>()
.setBit<p9hcd::CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT>()
.setBit<p9hcd::CPPM_CSAR_STOP_HCODE_ERROR_INJECT>();
// Note: CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP is NOT
// cleared as this is a persistent, characterization setting
// *INDENT-ON*
l_address = C_CPPM_CSAR_CLEAR;
FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64),
"ERROR: Failed to clear the CSAR register");

// Restore CORE PPM Error Mask
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CORE_PPM_ERRMASK,
l_core_chplt,
Expand Down
14 changes: 13 additions & 1 deletion src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,13 @@
// -----------------------------------------------------------------------------
// Constants
// -----------------------------------------------------------------------------
// @todo RTC 148540 Refine this values for the lab

// Map the auto generated names to clearer ones
static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1;
static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2;
static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1;
static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2;

// Following constants hold an approximate value.
static const uint32_t PGPE_TIMEOUT_MS = 500;
static const uint32_t PGPE_TIMEOUT_MCYCLES = 20;
Expand Down Expand Up @@ -157,6 +163,12 @@ fapi2::ReturnCode pstate_gpe_init(
.insertFromRight<4, 4>(0xA); // FIT
FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_GPETSEL_SCOM, l_data64));

// Clear error injection bits
l_data64.flush<0>()
.setBit<p9hcd::OCCFLG2_PGPE_HCODE_FIT_ERR_INJ>()
.setBit<p9hcd::OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ>();
FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64));

// Program XCR to ACTIVATE PGPE
FAPI_INF(" Starting the PGPE...");
l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1, 3);
Expand Down
20 changes: 12 additions & 8 deletions src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@
/// - call p9_pm_pba_init in PM_RESET mode to get the PBA in "boot" mode
/// - Read the SGPE IVPR value that is in HOMER from Attribute written
/// by p9_hcode_image_build
/// - Clear error injection bits
/// - Sreset the SGPE to start the boot copier from .
/// - Polls OCC Flag bit for HCode init completion
/// - Starting the SGPE will cause a "reboot" of functional CMEs
Expand Down Expand Up @@ -72,16 +73,15 @@
#include <p9_misc_scom_addresses_fld.H>
#include <p9n2_misc_scom_addresses.H>

//#include <p9_ppe_state.H> @todo RTC 147996 to incorporate PPE state removing strings.


// ----------------------------------------------------------------------
// Constants
// ----------------------------------------------------------------------

// Map the auto generated names to clearer ones
static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1;
static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2;
static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1;
static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2;
static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1;
static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2;

static const uint32_t SGPE_TIMEOUT_MS = 2500; // Guess at this time
static const uint32_t SGPE_TIMEOUT_MCYCLES = 20; // Guess at this time
Expand Down Expand Up @@ -317,18 +317,22 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
.insertFromRight<4, 4>(0xA); // FIT
FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_GPETSEL_SCOM, l_data64));

// Clear error injection bits
l_data64.flush<0>().setBit<p9hcd::OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ>();
FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64));

// Set the Malf Alert Enabled policy to OCCFLG2 reg bit 29
FAPI_IMP ("Malf Alert Policy Enabled: %d", malfAlertEnable);

l_data64.flush<0>().setBit<p9hcd::STOP_RECOVERY_TRIGGER_ENABLE>();

if (malfAlertEnable == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE)
{
FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM2, l_data64));
FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_SET, l_data64));
}
else
{
FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM1, l_data64));
FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64));
}

FAPI_IMP ("Malf Alert Policy Set to OCC FLAG2 .. now init SGPE");
Expand Down Expand Up @@ -540,7 +544,7 @@ fapi2::ReturnCode stop_gpe_reset(

FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register...");
l_data64.flush<0>().setBit<p9hcd::SGPE_ACTIVE>();
FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM1, l_data64));
FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_CLEAR, l_data64));

fapi_try_exit:
FAPI_IMP("<< stop_gpe_reset...");
Expand Down

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