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Adds LRDIMM DWL training step
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Change-Id: I0fe9a777722cec85249a558a37a90b1eaaf7cd0a
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67525
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68560
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@sglancy6 @dcrowell77
sglancy6 authored and dcrowell77 committed Nov 29, 2018
1 parent 9744e66 commit 546c014
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Showing 5 changed files with 100 additions and 93 deletions.
68 changes: 68 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
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Original file line number Diff line number Diff line change
Expand Up @@ -1517,6 +1517,40 @@ struct mrs06_data
fapi2::ReturnCode mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst);

///
/// @brief Sets WR LVL mode
/// @param[in] i_target a DIMM target
/// @param[in] i_mode setting for WR LVL mode
/// @param[in,out] io_data data we are modifying MPR mode to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
inline fapi2::ReturnCode set_wr_lvl_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const mss::states i_mode,
mrs01_data& io_data)
{
constexpr uint64_t MAX_WR_LVL_MODE = 0b1;

FAPI_ASSERT( i_mode <= MAX_WR_LVL_MODE,
fapi2::MSS_BAD_MR_PARAMETER()
.set_MR_NUMBER(MRS_LOAD)
.set_PARAMETER(WR_LVL)
.set_PARAMETER_VALUE(i_mode)
.set_DIMM_IN_ERROR(i_target),
"%s Invalid WR LVL Mode recieved: %d. Max encoding allowed: %d.",
mss::c_str(i_target),
i_mode,
MAX_WR_LVL_MODE);

// Update field if input check passes
io_data.iv_wl_enable = i_mode == mss::states::ON ?
fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE :
fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE;

return fapi2::FAPI2_RC_SUCCESS;
fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Set MPR Mode
/// @param[in] i_target a DIMM target
Expand Down Expand Up @@ -1683,6 +1717,40 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Makes CCS instruction to set WR LVL Mode
/// @tparam T TargetType of the CCS instruction
/// @param[in] i_target a DIMM target
/// @param[in] i_mode setting for WR LVL mode
/// @param[in] i_rank DIMM rank
/// @param[in,out] io_inst a vector of CCS instructions we should add to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
template< fapi2::TargetType T >
fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const mss::states i_mode,
const uint64_t i_rank,
std::vector< ccs::instruction_t<T> >& io_inst )
{
// Spec states we need to use tmod for our delay, so we do
const uint64_t l_delay = mss::tmod(i_target);

mrs01_data l_data(i_target, fapi2::current_err);
FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs01_data for set_wr_lvl_mode", mss::c_str(i_target) );

FAPI_TRY( set_wr_lvl_mode(i_target, i_mode, l_data),
"%s. Failed set_wr_lvl_mode() with a setting of %d",
mss::c_str(i_target), i_mode);

// Make MRS CCS inst
FAPI_TRY( mrs_engine(i_target, l_data, i_rank, l_delay, io_inst),
"Failed to send MRS01 on %s, rank: %d, delay (in cycles): %d",
mss::c_str(i_target), i_rank, l_delay);

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Makes CCS instruction to set MPR Mode
/// @tparam T TargetType of the CCS instruction
Expand Down
3 changes: 2 additions & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -69,6 +69,7 @@ enum mrs_bad_field
RTT_WR = 12,
MPR_PAGE = 13,
MPR_MODE = 14,
WR_LVL = 15,

// Following is for MR_NUMBER entry into the BAD_MR_PARAM ffdc
// Set to random value so it won't be confused with an actual MR number
Expand Down
43 changes: 3 additions & 40 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,8 @@
#include <lib/ccs/ccs.H>
#include <lib/mc/port.H>
#include <lib/rosetta_map/rosetta_map.H>
#include <lib/workarounds/ccs_workarounds.H>
#include <lib/dimm/ddr4/pba.H>

namespace mss
{
Expand All @@ -57,7 +59,6 @@ namespace training

namespace lrdimm
{

///
/// @brief Swizzles a DQ from the MC perspective to the DIMM perspective
/// @param[in] i_target the MCA target on which to operate
Expand Down Expand Up @@ -244,7 +245,7 @@ fapi_try_exit:
/// @param[in] i_target - the MCA target on which to operate
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok
///
fapi2::ReturnCode mrep::execute_nttm_mode_read(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) const
fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
{
mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program;
const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target);
Expand Down Expand Up @@ -687,44 +688,6 @@ uint64_t mrep::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_
return 0;
}

///
/// @brief Sets up and runs the calibration step
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode dwl::run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const
{
return fapi2::FAPI2_RC_SUCCESS;
}

///
/// @brief Executes a cal step with workarounds
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode dwl::execute( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const
{
return fapi2::FAPI2_RC_SUCCESS;
}

///
/// @brief Calculates the number of cycles a given calibration step will take
/// @param[in] i_target - the MCA target on which to operate
/// @return l_cycles - the number of cycles a given calibration step wil take
///
uint64_t dwl::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
{
return 0;
}

///
/// @brief Sets up and runs the calibration step
/// @param[in] i_target - the MCA target on which to operate
Expand Down
64 changes: 12 additions & 52 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,11 @@
#include <lib/workarounds/ccs_workarounds.H>
#include <lib/rosetta_map/rosetta_map.H>

// Disables LRDIMM support for HB
#ifndef __HOSTBOOT_MODULE
#define LRDIMM_CAPABLE 1
#endif

namespace mss
{

Expand Down Expand Up @@ -463,13 +468,6 @@ class mrep : public step
i_mrep_result,
mss::ddr4::pba::commands& o_container) const;

///
///// @brief Does a CCS NTTM mode read
///// @param[in] i_target - the MCA target on which to operate
///// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok
/////
fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) const;

///
/// @brief analyze with each nibble
/// @param[in] i_target the MCA target
Expand Down Expand Up @@ -609,51 +607,6 @@ class mrep : public step

};

///
/// @brief DWL training step
///
class dwl : public step
{
public:
dwl() :
step("DWL")
{}

///
/// @brief Default virtual destructor
///
~dwl() = default;

///
/// @brief Sets up and runs the calibration step
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const;

///
/// @brief Executes a cal step with workarounds
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const;

///
/// @brief Calculates the number of cycles a given calibration step will take
/// @param[in] i_target - the MCA target on which to operate
/// @return l_cycles - the number of cycles a given calibration step wil take
///
uint64_t calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const;
};

///
/// @brief MPR training step
///
Expand Down Expand Up @@ -833,6 +786,13 @@ void deconfigure_steps(const uint8_t i_dimm_type,
const bool i_sim,
fapi2::buffer<uint32_t>& io_cal_steps);

///
/// @brief Does a CCS NTTM mode read
/// @param[in] i_target - the MCA target on which to operate
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok
///
fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);

} // ns training

} // ns lrdimm
Expand Down
15 changes: 15 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,10 @@
#include <lib/phy/seq.H>
#include <lib/phy/read_cntrl.H>

#ifdef LRDIMM_CAPABLE
#include <lib/phy/mss_dwl.H>
#endif

namespace mss
{

Expand Down Expand Up @@ -1221,6 +1225,17 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>&
l_steps.push_back(std::make_shared<mss::training::lrdimm::mrep>());
}

#ifdef LRDIMM_CAPABLE

// DWL
if(i_cal_steps.getBit<mss::cal_steps::DWL>())
{
FAPI_INF("LRDIMM: DWL is enabled");
l_steps.push_back(std::make_shared<mss::training::lrdimm::dwl>());
}

#endif

// WR LVL
if(i_cal_steps.getBit<mss::cal_steps::WR_LEVEL>())
{
Expand Down

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