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Adds DD2 dcd functionality
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Change-Id: I2d873ea84b8ae202d78cf8c49ffce56caebd3699
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41052
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41054
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@sglancy6 @dcrowell77
sglancy6 authored and dcrowell77 committed Jun 11, 2017
1 parent 4ffb8a8 commit 582e6b3
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Showing 7 changed files with 857 additions and 410 deletions.
17 changes: 17 additions & 0 deletions src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H
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Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,11 @@ static const uint64_t SH_FLD_23_DD2_PERBIT_RDVREF_DISABLE = 99990099;
static const uint64_t SH_FLD_4_DD2_PERBIT_RDVREF_DISABLE = 99990100;
static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE = 99990101;
static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN = 99990102;
static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN = 99990103;
static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE = 99990104;
static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN = 99990105;
static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE = 99990106;
static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR = 99990107;

REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
0 );
Expand Down Expand Up @@ -589,4 +594,16 @@ REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE , 48 , SH
SH_FLD_01_DD2_BLUE_EXTEND_RANGE );
REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN );

// DCD DD2 field updates
REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN );
REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE );
REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN );
REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE );
REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW ,
SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR );
#endif
28 changes: 12 additions & 16 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
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Original file line number Diff line number Diff line change
Expand Up @@ -27,16 +27,18 @@
/// @file adr32s.C
/// @brief Subroutines for the PHY ADR32S registers
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
#include <lib/phy/adr32s.H>
#include <lib/phy/dcd.H>
#include <lib/workarounds/adr32s_workarounds.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/mss_attribute_accessors_manual.H>

using fapi2::TARGET_TYPE_MCA;
using fapi2::TARGET_TYPE_SYSTEM;
Expand Down Expand Up @@ -83,10 +85,7 @@ namespace adr32s
///
fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target )
{
typedef adr32sTraits<TARGET_TYPE_MCA> TT;

const auto l_mca = mss::find_targets<TARGET_TYPE_MCA>(i_target);
fapi2::buffer<uint64_t> l_read;
uint8_t l_sim = 0;

FAPI_TRY( mss::is_simulation( l_sim) );
Expand All @@ -110,21 +109,18 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::
return FAPI2_RC_SUCCESS;
}

// Do a quick check to make sure this chip doesn't have the DCD logic built in (e.g., DD1 Nimbus)
// TODO RTC:159687 For DD2 all we need to do is kick off the h/w cal and wait. We can check any ADR_DCD
// register, they all should reflect the inclusion of the DCD logic.

FAPI_TRY( mss::getScom(l_mca[0], TT::DUTY_CYCLE_DISTORTION_REG[0], l_read) );

if (l_read.getBit<TT::DCD_CONTROL_DLL_CORRECT_EN>() == 1)
// Runs the proper DCD calibration for Nimbus DD1 vs DD2
if(mss::chip_ec_nimbus_lt_2_0(i_target))
{
FAPI_ERR("seeing ADR DCD algorithm is in the logic but we didn't code it?");
fapi2::Assert(false);
// Runs the DD1 calibration
FAPI_TRY(mss::workarounds::adr32s::duty_cycle_distortion_calibration(i_target));
}

// Runs the DD1 algorithm for now. The below TODO is to add in a switch to the DD2 algorithm
// TODO RTC:159687 For DD2 all we need to do is kick off the h/w cal and wait. We can check any ADR_DCD
FAPI_TRY(mss::workarounds::adr32s::duty_cycle_distortion_calibration(i_target));
else
{
// Runs the DD2 calibration algorithm
FAPI_TRY(mss::dcd::execute_hw_calibration(i_target));
}

fapi_try_exit:
return fapi2::current_err;
Expand Down

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