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Unmask after draminit and draminit_mc; cmd complete
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- Define after_* functions and unmasking operations
- Add FAPI_TRY calls to after_* functions in exp_draminit files
- Add SRQFIR, MCBISTFIR, and RDFFIR register traits to exp_fir_traits.H
- after_draminit and after_draminit_mc unit tests

Change-Id: Ie7e6fcfd4b71259e88ad1f804b3da015c9faabf1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89488
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: NICOLAS R FAJARDO <nicolas.fajardo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Marc Gollub <gollub@us.ibm.com>
Reviewed-by: Caleb N Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89525
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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NicoFajardo authored and dcrowell77 committed Jan 29, 2020
1 parent 6b29b38 commit 5962066
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/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* Contributors Listed Below - COPYRIGHT 2018,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
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#include <lib/phy/exp_train_handler.H>
#include <lib/shared/exp_consts.H>
#include <generic/memory/mss_git_data_helper.H>
#include <generic/memory/lib/utils/fir/gen_mss_unmask.H>

extern "C"
{
Expand Down Expand Up @@ -86,6 +87,9 @@ extern "C"
FAPI_TRY(mss::exp::host_fw_phy_init_with_eye_capture(i_target, l_crc, l_phy_params));
}

// Unmask registers after draminit training
FAPI_TRY(mss::unmask::after_draminit_training(i_target), "%s Failed after_draminit_training", mss::c_str(i_target));

return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* Contributors Listed Below - COPYRIGHT 2018,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -41,6 +41,7 @@

#include <lib/mc/exp_port.H>
#include <generic/memory/mss_git_data_helper.H>
#include <generic/memory/lib/utils/fir/gen_mss_unmask.H>

extern "C"
{
Expand Down Expand Up @@ -97,9 +98,8 @@ extern "C"
// Apply marks from OCMB VPD
FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );

// TODO: Move mss::unmask::after_draminit_mc to generic and call it
// At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked.
//FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) );
// Unmask registers after draminit_mc
FAPI_TRY(mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target));

fapi_try_exit:
FAPI_INF("%s End exp_draminit MC", mss::c_str(i_target));
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -44,5 +44,5 @@ namespace mss

// FIR Register Traits for Explorer will be here sooner or later.

}
} // end mss ns
#endif
Expand Up @@ -22,3 +22,78 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file exp_fir_traits.H
/// @brief Memory subsystem FIR support
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#ifndef _MSS_EXP_FIR_TRAITS_H_
#define _MSS_EXP_FIR_TRAITS_H_

#include <fapi2.H>
#include <generic/memory/lib/utils/fir/gen_mss_fir.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <explorer_scom_addresses.H>
#include <explorer_scom_addresses_fld.H>

namespace mss
{

///
/// @brief FIR Register Traits for Explorer MCBIST FIR
///
template <>
struct firTraits<EXPLR_MCBIST_MCBISTFIRQ>
{
static constexpr uint64_t REG = EXPLR_MCBIST_MCBISTFIRQ;
static constexpr uint64_t ACT0 = EXPLR_MCBIST_MCBISTFIRACT0;
static constexpr uint64_t ACT1 = EXPLR_MCBIST_MCBISTFIRACT1;
static constexpr uint64_t MASK = EXPLR_MCBIST_MCBISTFIRMASK;
static constexpr uint64_t MASK_AND = EXPLR_MCBIST_MCBISTFIRMASK_AND;
static constexpr uint64_t MASK_OR = EXPLR_MCBIST_MCBISTFIRMASK_OR;

// Target type of this register
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP;
};

///
/// @brief FIR Register Traits for Explorer SRQ FIR
///
template <>
struct firTraits<EXPLR_SRQ_SRQFIRQ>
{
static constexpr uint64_t REG = EXPLR_SRQ_SRQFIRQ;
static constexpr uint64_t ACT0 = EXPLR_SRQ_SRQFIR_ACTION0;
static constexpr uint64_t ACT1 = EXPLR_SRQ_SRQFIR_ACTION1;
static constexpr uint64_t MASK = EXPLR_SRQ_SRQFIR_MASK;
static constexpr uint64_t MASK_AND = EXPLR_SRQ_SRQFIR_MASK_AND;
static constexpr uint64_t MASK_OR = EXPLR_SRQ_SRQFIR_MASK_OR;

// Target type of this register
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP;
};

///
/// @brief FIR Register Traits for Explorer RDF FIR
///
template <>
struct firTraits<EXPLR_RDF_FIR>
{
static constexpr uint64_t REG = EXPLR_RDF_FIR;
static constexpr uint64_t ACT0 = EXPLR_RDF_ACTION0;
static constexpr uint64_t ACT1 = EXPLR_RDF_ACTION1;
static constexpr uint64_t MASK = EXPLR_RDF_MASK;
static constexpr uint64_t MASK_AND = EXPLR_RDF_MASK_AND;
static constexpr uint64_t MASK_OR = EXPLR_RDF_MASK_OR;

// Target type of this register
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP;
};

} // end mss ns
#endif
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -23,7 +23,7 @@
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file unmask.C
/// @file exp_unmask.C
/// @brief Subroutines for unmasking and setting up MSS FIR
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
Expand All @@ -38,6 +38,7 @@
#include <explorer_scom_addresses_fld.H>
#include <generic/memory/lib/utils/scom.H>
#include <lib/fir/exp_fir.H>
#include <lib/fir/exp_fir_traits.H>
#include <generic/memory/lib/utils/fir/gen_mss_unmask.H>

namespace mss
Expand All @@ -50,24 +51,103 @@ namespace unmask
/// @brief Unmask and setup actions performed after draminit_mc
/// @param[in] i_target the fapi2::Target
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
/// TODO: Need to implement this function
///
template<>
fapi2::ReturnCode after_draminit_mc<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
i_target )
{
fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc3 = fapi2::FAPI2_RC_SUCCESS;

// Create registers and check success for MCBISTFIR and SRQFIR and RDFFIR
mss::fir::reg<EXPLR_MCBIST_MCBISTFIRQ> l_exp_mcbist_reg(i_target, l_rc1);
mss::fir::reg<EXPLR_SRQ_SRQFIRQ> l_exp_srq_reg(i_target, l_rc2);
mss::fir::reg<EXPLR_RDF_FIR> l_exp_rdf_reg(i_target, l_rc3);

FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ);
FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ);
FAPI_TRY(l_rc3, "unable to create fir::reg for %d", EXPLR_RDF_FIR);

// Write MCBISTFIR register per Explorer unmask spec
FAPI_TRY(l_exp_mcbist_reg.attention<EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE>()
.write());

// Write RDF FIR register per Explorer unmask spec
// TK Need to set EXPLR_RDF_FIR_MAINTENANCE_RCD to recoverable for planar/ISDIMM
FAPI_TRY(l_exp_rdf_reg.recoverable_error<EXPLR_RDF_FIR_MAINTENANCE_AUE>()
.recoverable_error<EXPLR_RDF_FIR_MAINTENANCE_IAUE>()
.recoverable_error<EXPLR_RDF_FIR_RDDATA_VALID_ERROR>()
.recoverable_error<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_STATUS>()
.recoverable_error<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE>()
.checkstop<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE>()
.checkstop<EXPLR_RDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR>()
.recoverable_error<EXPLR_RDF_FIR_ECC_RBUF_CE_DW0>()
.recoverable_error<EXPLR_RDF_FIR_ECC_RBUF_CE_DW1>()
.checkstop<EXPLR_RDF_FIR_ECC_RBUF_UE_DW0>()
.checkstop<EXPLR_RDF_FIR_ECC_RBUF_UE_DW1>()
.write());

// Write SRQ FIR register per Explorer unmask spec
FAPI_TRY(l_exp_srq_reg.recoverable_error<EXPLR_SRQ_SRQFIRQ_REFRESH_OVERRUN>()
.write());

return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:

FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err);
return fapi2::current_err;
}

///
/// @brief Unmask and setup actions performed after draminit_training
/// @param[in] i_target the fapi2::Target
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
/// TODO: Need to implement this function
///
template<>
fapi2::ReturnCode after_draminit_training<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
i_target )
{
fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS;

// Create registers and check success for MCBISTFIR and SRQFIR
mss::fir::reg<EXPLR_MCBIST_MCBISTFIRQ> l_exp_mcbist_reg(i_target, l_rc1);
mss::fir::reg<EXPLR_SRQ_SRQFIRQ> l_exp_srq_reg(i_target, l_rc2);

FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ);
FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ);

// Write MCBISTFIR register per Explorer unmask spec; omit bit 10 cmd_complete until draminit_mc
FAPI_TRY(l_exp_mcbist_reg.recoverable_error<EXPLR_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT>()
.checkstop<EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR>()
.checkstop<EXPLR_MCBIST_MCBISTFIRQ_CCS_ARRAY_UNCORRECT_CE_OR_UE>()
.recoverable_error<EXPLR_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE>()
.checkstop<EXPLR_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE>()
.write());

// Write SRQ FIR register per Explorer unmask spec
FAPI_TRY(l_exp_srq_reg.recoverable_error<EXPLR_SRQ_SRQFIRQ_NCF_MCB_LOGIC_ERROR>()
.checkstop<EXPLR_SRQ_SRQFIRQ_NCF_MCB_PARITY_ERROR>()
.recoverable_error<EXPLR_SRQ_SRQFIRQ_WRQ_RRQ_HANG_ERR>()
.checkstop<EXPLR_SRQ_SRQFIRQ_SM_1HOT_ERR>()
.checkstop<EXPLR_SRQ_SRQFIRQ_CMD_PARITY_ERROR>()
.checkstop<EXPLR_SRQ_SRQFIRQ_WDF_ERROR2>()
.checkstop<EXPLR_SRQ_SRQFIRQ_WDF_ERROR3>()
.recoverable_error<EXPLR_SRQ_SRQFIRQ_WDF_ERROR7>()
.checkstop<EXPLR_SRQ_SRQFIRQ_NCF_UE>()
.checkstop<EXPLR_SRQ_SRQFIRQ_NCF_LOGIC_ERROR>()
.checkstop<EXPLR_SRQ_SRQFIRQ_NCF_PARITY_ERROR>()
.recoverable_error<EXPLR_SRQ_SRQFIRQ_NCF_CORR_ERROR>()
.write());

return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:

FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err);
return fapi2::current_err;
}

///
Expand Down Expand Up @@ -115,5 +195,5 @@ fapi2::ReturnCode after_background_scrub<mss::mc_type::EXPLORER>( const fapi2::T
return fapi2::FAPI2_RC_SUCCESS;
}

}
}
} // end unmask ns
} // end mss ns

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