Inverted logic of hasClock bit in Clock Status register

CQ: SW437571
Change-Id: I9101adc63225a97aeddf445519fa660d961c3d9c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62335
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62360
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/pm/p9_query_core_access_state.C

@@ -175,7 +175,11 @@ p9_query_core_access_state(
             FAPI_TRY(fapi2::getScom(i_target, C_CLOCK_STAT_SL,  l_data64), "Error reading data from C_CLOCK_STAT_SL");
 
             l_data64.extractToRight<uint8_t>(c_exec_hasclocks, 6, 1);
+            // Inverted logic in the HW
+            c_exec_hasclocks = !c_exec_hasclocks;
             l_data64.extractToRight<uint8_t>(c_pc_hasclocks,   5, 1);
+            // Inverted logic in the HW
+            c_pc_hasclocks = !c_pc_hasclocks;
         }
         else
         {