Adds explorer Per DRAM Addressability

Change-Id: I6019a001a40f41e501e26974f13df9c0790fb97d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94883
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/96153
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C

@@ -33,8 +33,10 @@
 // *HWP Level: 2
 // *HWP Consumed by: FSP:HB
 
-#include <lib/shared/exp_consts.H>
 #include <lib/shared/exp_defaults.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <lib/dimm/exp_mrs_traits.H>
 #include <lib/inband/exp_inband.H>
 #include <generic/memory/lib/utils/c_str.H>
 #include <generic/memory/lib/utils/mss_bad_bits.H>

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_explorer.C

@@ -25,7 +25,7 @@
 
 ///
 /// @file mrs_load_ddr4_explorer.C
-/// @brief Specializations for Explorer's MRS code
+/// @brief Run and manage the DDR4 mrs loading
 ///
 // *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
@@ -64,6 +64,7 @@ fapi2::ReturnCode is_a17_needed<mss::mc_type::EXPLORER>(const fapi2::Target<fapi
 
     o_is_needed = (l_dram_density == fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G
                    && l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4);
+
     FAPI_INF("%s Turning A17 %s", mss::c_str(i_target), o_is_needed ? "on" : "off" );
 
 fapi_try_exit:
@@ -72,7 +73,7 @@ fapi_try_exit:
 
 ///
 /// @brief Helper function to determine whether the A17 is needed
-/// @param[in] i_target the MCA target
+/// @param[in] i_target the MEM_PORT target
 /// @param[out] o_is_needed boolean whether A17 should be turned on or off
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
 /// @note Based off of Table 2.8 Proposed DDR4 Full spec update(79-4B) page 28

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C

@@ -36,6 +36,7 @@
 #include <fapi2.H>
 #include <lib/shared/exp_defaults.H>
 #include <lib/shared/exp_consts.H>
+#include <lib/shared/exp_defaults.H>
 #include <exp_data_structs.H>
 #include <generic/memory/lib/utils/mss_bad_bits.H>
 #include <generic/memory/lib/utils/endian_utils.H>

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.C

@@ -38,6 +38,7 @@
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
 #include <lib/shared/mss_const.H>
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
 #include <lib/mc/port.H>
 
 #include <generic/memory/lib/utils/c_str.H>
@@ -64,7 +65,7 @@ namespace pda
 {
 
 const std::vector<std::pair<uint64_t, uint64_t>>
-        pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, mss::mc_type::NIMBUS>::BIT_MAP =
+        pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4>::BIT_MAP =
 {
     {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
     {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
@@ -91,7 +92,7 @@ const std::vector<std::pair<uint64_t, uint64_t>>
 };
 
 const std::vector<std::pair<uint64_t, uint64_t>>
-        pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, mss::mc_type::NIMBUS>::BIT_MAP =
+        pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8>::BIT_MAP =
 {
     {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
     {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},
@@ -115,10 +116,9 @@ const std::vector<std::pair<uint64_t, uint64_t>>
 /// @param[in] i_state - the state to write the bit(s) to
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
-template< >
-fapi2::ReturnCode change_dram_bit<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        const uint64_t i_dram,
-        const mss::states& i_state)
+fapi2::ReturnCode change_dram_bit( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                                   const uint64_t i_dram,
+                                   const mss::states& i_state)
 {
     uint8_t l_dram_width[MAX_DIMM_PER_PORT] = {0};
     FAPI_TRY(mss::eff_dram_width(i_target, &(l_dram_width[0])), "Failed to get the DRAM's width for %s",
@@ -348,8 +348,7 @@ fapi_try_exit:
 /// @note A PDA latch of WR VREF settings is the most common PDA operations
 /// This function adds a bit of fanciness (compression) to speed up the overall runtime
 ///
-template<>
-fapi2::ReturnCode execute_wr_vref_latch<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         const uint64_t i_rank,
         const mss::ddr4::mrs06_data<mss::mc_type::NIMBUS>& i_mrs,
         const std::vector<uint64_t>& i_drams )
@@ -408,7 +407,7 @@ fapi2::ReturnCode execute_wr_vref_latch<mss::mc_type::NIMBUS>( const
     // If the commands passed in are empty, simply exit
     FAPI_ASSERT((!i_commands.empty()),
                 fapi2::MSS_EMPTY_PDA_VECTOR().
-                set_PROCEDURE(mss::ffdc_function_codes::PDA_WR_VREF_LATCH_CONTAINER),
+                set_PROCEDURE(mss::generic_ffdc_codes::PDA_WR_VREF_LATCH_CONTAINER),
                 "PDA commands map is empty, exiting");
 
     // Loop until all commands have been issued

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.H

@@ -76,11 +76,19 @@ enum consts : uint64_t
     DRAM_START = DRAM0,
 };
 
+///
+/// @class pdaBitTraits
+/// @brief Write bit traits class
+/// @tparam W the DRAM's width
+///
+template < uint8_t W >
+class pdaBitTraits;
+
 ///
 /// @brief Write bit for PDA specialization for x4 devices
 ///
 template < >
-class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, mss::mc_type::NIMBUS>
+class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4>
 {
     public:
         // One nibble is needed - the register has one nibble per bit, so one bit
@@ -93,7 +101,7 @@ class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, mss::mc_type::NIMBUS>
 /// @brief Write bit for PDA specialization for x8 devices
 ///
 template < >
-class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, mss::mc_type::NIMBUS>
+class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8>
 {
     public:
         // Two nibbles are needed - the register has one nibble per bit, so two bits
@@ -102,6 +110,167 @@ class pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, mss::mc_type::NIMBUS>
         static const std::vector<std::pair<uint64_t, uint64_t>> BIT_MAP;
 };
 
+///
+/// @brief PDA traits class
+/// @tparam MC the memory controller type
+///
+template<>
+class pda_traits<mss::mc_type::NIMBUS>
+{
+    public:
+        typedef std::pair<fapi2::Target<fapi2::TARGET_TYPE_DIMM>, uint64_t> RANK_TARGET;
+
+        ///
+        /// @brief Gets the rank target information for PDA
+        /// @param[in] i_target MCA target
+        /// @param[in] i_rank rank on which to operate
+        /// @param[out] o_rank_target the rank target for this MCA/rank
+        ///
+        static fapi2::ReturnCode get_rank_target(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                const uint64_t i_rank,
+                RANK_TARGET& o_rank_target)
+        {
+            fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm;
+            FAPI_TRY(mss::rank::get_dimm_target_from_rank(i_target,
+                     i_rank,
+                     l_dimm));
+
+            // Check for a valid rank
+            FAPI_ASSERT(mss::rank::is_rank_on_dimm(l_dimm, i_rank),
+                        fapi2::MSS_INVALID_RANK().
+                        set_PORT_TARGET(i_target).
+                        set_RANK(i_rank).
+                        set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND),
+                        "%s does not have rank %lu", mss::c_str(i_target), i_rank);
+
+            o_rank_target = {l_dimm, i_rank};
+
+            return fapi2::FAPI2_RC_SUCCESS;
+        fapi_try_exit:
+            return fapi2::current_err;
+
+        }
+
+        ///
+        /// @brief Gets the rank target information for PDA
+        /// @param[in] i_target DIMM target
+        /// @param[in] i_rank rank on which to operate
+        /// @param[out] o_rank_target the rank target for this MCA/rank
+        ///
+        static fapi2::ReturnCode get_rank_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                const uint64_t i_rank,
+                RANK_TARGET& o_rank_target)
+        {
+            // Check for a valid rank
+            FAPI_ASSERT(mss::rank::is_rank_on_dimm(i_target, i_rank),
+                        fapi2::MSS_INVALID_RANK().
+                        set_PORT_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)).
+                        set_RANK(i_rank).
+                        set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND),
+                        "%s does not have rank %lu", mss::c_str(i_target), i_rank);
+
+            o_rank_target = {i_target, i_rank};
+
+            return fapi2::FAPI2_RC_SUCCESS;
+        fapi_try_exit:
+            return fapi2::current_err;
+
+        }
+
+};
+
+///
+/// @brief Sets the enable bit for a dram
+/// @tparam D the DRAM to enable or disable
+/// @param[in,out] io_data the data buffer to modify
+/// @param[in] i_state the state to modify the buffer to
+///
+template< uint64_t D >
+inline void set_dram_enable( fapi2::buffer<uint64_t>& io_data, const mss::states& i_state)
+{
+    io_data.writeBit<D>(i_state);
+}
+
+///
+/// @brief Enters into and configures PDA mode
+/// @param[in] i_target a fapi2::Target DIMM
+/// @param[in] i_rank the rank to send to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                         const uint64_t i_rank );
+
+///
+/// @brief Exits out of and disables PDA mode
+/// @param[in] i_target a fapi2::Target DIMM
+/// @param[in] i_rank the rank to send to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                        const uint64_t i_rank );
+
+///
+/// @brief Helper function for changing the DRAM bit
+/// @tparam W the DRAM width
+/// @tparam TT the DRAM width traits class
+/// @param[in] i_target - the MCA target
+/// @param[in] i_dram - the DRAM on which to operate
+/// @param[in] i_state - the state to write the bit(s) to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template< uint8_t W, typename TT = pdaBitTraits<W> >
+fapi2::ReturnCode change_dram_bit_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        const uint64_t i_dram,
+        const mss::states& i_state)
+{
+    fapi2::buffer<uint64_t> l_data;
+
+    // Note: the following avoids "undefined reference to" errors due to the set max dram below
+    // The use of traits and a const reference messes with it
+    constexpr auto NUM_DRAM = TT::NUM_DRAMS;
+
+    // Check bounds
+    FAPI_ASSERT(i_dram < NUM_DRAM,
+                fapi2::MSS_PDA_DRAM_OUT_OF_RANGE().
+                set_TARGET(i_target).
+                set_DRAM(i_dram).
+                set_MAX_DRAM(NUM_DRAM),
+                "%s was passed DRAM value of %lu which is not below the max value of %lu",
+                mss::c_str(i_target), i_dram, NUM_DRAM);
+
+    FAPI_TRY(mss::getScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
+    FAPI_TRY(l_data.writeBit(i_state, TT::BIT_MAP[i_dram].second, TT::NUM_BITS));
+    FAPI_TRY(mss::putScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Writes the data bit enable for the properly inputted DRAM
+/// @param[in] i_target - the MCA target
+/// @param[in] i_dram - the DRAM on which to operate
+/// @param[in] i_state - the state to write the bit(s) to
+/// @note PDA is LOW enable, so 0's means ON. ON will configure the register to 0's
+///
+fapi2::ReturnCode change_dram_bit( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                                   const uint64_t i_dram,
+                                   const mss::states& i_state);
+
+///
+/// @brief Performs a PDA WR VREF latch
+/// @param[in] i_target a fapi2::Target DIMM
+/// @param[in] i_rank the rank to send to
+/// @param[in] i_mrs the MRS data to update
+/// @param[in] i_drams the DRAM to update
+/// @return FAPI2_RC_SUCCESS if and only if ok
+/// @note A PDA latch of WR VREF settings is the most common PDA operations
+/// This function adds a bit of fanciness (compression) to speed up the overall runtime
+///
+fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const uint64_t i_rank,
+        const mss::ddr4::mrs06_data<mss::mc_type::NIMBUS>& i_mrs,
+        const std::vector<uint64_t>& i_drams );
 
 ///
 /// @brief Configures PDA timings
@@ -119,6 +288,41 @@ void configure_timings( fapi2::buffer<uint64_t>& io_buffer );
 ///
 fapi2::ReturnCode configure_timings_and_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
+///
+/// @brief Configures all DRAM level configuration bits to the inputted settings
+/// @tparam MC mss::mc_type memory controller type
+/// @tparam TT traits type defaults to mrsTraits<MC>
+/// @param[in] i_target a fapi2::Target MCA
+/// @param[in] i_state - OFF - 1's, ON - 0's
+/// @return FAPI2_RC_SUCCESS if and only if ok
+/// @note PDA is LOW enable, so 0's means ON. ON will configure the register to 0's
+///
+template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits<MC> >
+fapi2::ReturnCode blast_dram_config( const fapi2::Target<TT::PORT_TARGET_TYPE>& i_target,
+                                     const mss::states& i_state );
+
+///
+/// @brief Adds a PDA enable command
+/// @param[in] i_target a fapi2::Target DIMM
+/// @param[in] i_rank the rank to send to
+/// @param[in,out] io_inst the CCS instructions to update
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                              const uint64_t i_rank,
+                              std::vector< ccs::instruction_t >& io_inst );
+
+///
+/// @brief Adds a PDA disable command
+/// @param[in] i_target a fapi2::Target DIMM
+/// @param[in] i_rank the rank to send to
+/// @param[in,out] io_inst the CCS instructions to update
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+                               const uint64_t i_rank,
+                               std::vector< ccs::instruction_t >& io_inst );
+
 } // ns pda
 
 } // ns ddr4

src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C

@@ -67,6 +67,7 @@ namespace training
 
 namespace lrdimm
 {
+
 ///
 /// @brief Swizzles a DQ from the MC perspective to the DIMM perspective
 /// @param[in] i_target the MCA target on which to operate

src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H

@@ -129,7 +129,6 @@ enum ffdc_function_codes
     MAP_RP_PRIMARY_TO_INIT_CAL = 60,
 
     // PDA function codes
-    PDA_WR_VREF_LATCH_CONTAINER = 80,
     PDA_WR_VREF_LATCH_VECTOR = 81,
     PDA_ADD_COMMAND = 82,
 

src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml

@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2019                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2020                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -466,28 +466,6 @@
     </callout>
   </hwpError>
 
-  <hwpError>
-    <rc>RC_MSS_EMPTY_PDA_VECTOR</rc>
-    <description>Indicates a that a vector was empty when a procedure was called</description>
-    <ffdc>PROCEDURE</ffdc>
-    <callout>
-      <procedure>CODE</procedure>
-      <priority>HIGH</priority>
-    </callout>
-  </hwpError>
-
-  <hwpError>
-    <rc>RC_MSS_PDA_DRAM_OUT_OF_RANGE</rc>
-    <description>Indicates a DRAM passed to the PDA code is out of range</description>
-    <ffdc>MCA_TARGET</ffdc>
-    <ffdc>DRAM</ffdc>
-    <ffdc>MAX_DRAM</ffdc>
-    <callout>
-      <procedure>CODE</procedure>
-      <priority>HIGH</priority>
-    </callout>
-  </hwpError>
-
   <hwpError>
     <rc>RC_MSS_SELECT_PORT_MCA_OUT_OF_RANGE</rc>
     <description>Indicates a MCA is out of range</description>