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FBC ABUS TDM inject and recovery HWPs
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p9_fbc_ioo_tdm_inject
  New HWP to permit concurrent maintenance of an SMP OBUS link
  (full-width to half-width operation)

  Specified half-link of provided endpoint target will have:
    - FIRs masked
    - DL layer quiesced
    - PHY powered down

  FW should set i_opts members as follows:
    - i_opts.run_all=true                    -- HWP executes all steps
    - i_opts.step=P9_FBC_IOO_TDM_INJECT_END  -- don't care

p9_fbc_ioo_tdm_recovery
  New HWP to permit concurrent maintenance of an SMP OBUS link
  (half-width to full-width operation)

  HWP detects half-link to recover from provided enpoint target. Specified
  half-link will have:
    - FIRs masked and reset
    - DL layer reset
    - PHY layer reset, dccal run, and re-initialized
    - DL FIRs cleared
    - DL started and retrained
    - FIRs unmasked

  FW should set i_opts members as follows:
   - i_opts.run_all=true                     -- HWP executes all steps
   - i_opts.even_not_odd=true                -- don't care
   - i_opts.step=P9_FBC_IOO_TDM_RECOVERY_END -- don't care

p9_security_white_black_list
  Add greylist entries for OBUS PHY, DL layer FIR and FIR mask registers

p9_io_regs
  Add register constants needed for link recovery

p9_io_obus_reset
  Clear RX and TX ioreset
  Add inits specified in SCOM initfile used at initial IPL

p9_obus_fir_utils
  Add constants to reflect grey list entries for OBUS FIRs

p9_io_obus_scominit
p9_chiplet_scominit
  Reference p9_obus_fir_utils for OBUS FIR programming values

Change-Id: Iad3884f6057c2ca21f436bc6efc0423fb5f70226
CQ: SW446137
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59370
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/60829
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jjmcgill @dcrowell77
jjmcgill authored and dcrowell77 committed Sep 23, 2018
1 parent 5a2e55b commit 69cc45d
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60 changes: 45 additions & 15 deletions src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -535,6 +535,7 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
fapi2::ATTR_LINK_TRAIN_Type l_link_train;
fapi2::ATTR_CHIP_EC_FEATURE_HW419022_Type l_hw419022;
fapi2::ATTR_IO_OBUS_PAT_A_DETECT_RUN_Type l_pat_a_detect_run;
fapi2::ATTR_IO_OBUS_TRAIN_FOR_RECOVERY_Type l_train_for_recovery;
bool l_even = true;
bool l_odd = true;

Expand Down Expand Up @@ -568,6 +569,11 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
l_link_train),
"Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN)");

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_OBUS_TRAIN_FOR_RECOVERY,
i_tgt,
l_train_for_recovery),
"Error from FAPI_ATTR_GET (ATTR_IO_OBUS_TRAIN_FOR_RECOVERY)");

// determine link train capabilities (half/full)
l_even = (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH) ||
(l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY);
Expand Down Expand Up @@ -615,24 +621,27 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
PATTERN_A),
"Error from force_dl_pattern_send, pattern A, remote end");

// power down any unneeded lanes (not physically connected or
// at IPL time, power down any unneeded lanes (not physically connected or
// unused half-link)
for (uint8_t ii = 0; ii < MAX_LANES; ii++)
if (!l_train_for_recovery)
{
if (((ii >= ((MAX_LANES / 2) - 1)) && (ii <= (MAX_LANES / 2))) || // unused lanes, always pdwn
(!l_even && (ii < ((MAX_LANES / 2) - 1))) || // even link is unused
(!l_odd && (ii >= ((MAX_LANES / 2) + 1)))) // odd link is unused
for (uint8_t ii = 0; ii < MAX_LANES; ii++)
{
FAPI_TRY(pdwn_bad_lane(i_tgt,
GRP0,
ii),
"Error from pdwn_bad_lane, even, local end, lane: %d",
ii);
FAPI_TRY(pdwn_bad_lane(l_rem_tgt,
GRP0,
ii),
"Error from pdwn_bad_lane, even, remote end, lane: %d",
ii);
if (((ii >= ((MAX_LANES / 2) - 1)) && (ii <= (MAX_LANES / 2))) || // unused lanes, always pdwn
(!l_even && (ii < ((MAX_LANES / 2) - 1))) || // even link is unused
(!l_odd && (ii >= ((MAX_LANES / 2) + 1)))) // odd link is unused
{
FAPI_TRY(pdwn_bad_lane(i_tgt,
GRP0,
ii),
"Error from pdwn_bad_lane, even, local end, lane: %d",
ii);
FAPI_TRY(pdwn_bad_lane(l_rem_tgt,
GRP0,
ii),
"Error from pdwn_bad_lane, even, remote end, lane: %d",
ii);
}
}
}

Expand Down Expand Up @@ -696,6 +705,27 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
l_dl_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
}

FAPI_TRY(fapi2::putScomUnderMask(i_tgt,
OBUS_LL0_IOOL_CONTROL,
l_dl_control_data,
l_dl_control_mask),
"Error writing DLL control register (0x%08X)!",
OBUS_LL0_IOOL_CONTROL);

if (l_even && l_train_for_recovery)
{
l_dl_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
l_dl_control_mask.clearBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
l_dl_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
}

if (l_odd && l_train_for_recovery)
{
l_dl_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
l_dl_control_mask.clearBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
l_dl_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
}

FAPI_TRY(fapi2::putScomUnderMask(i_tgt,
OBUS_LL0_IOOL_CONTROL,
l_dl_control_data,
Expand Down
31 changes: 31 additions & 0 deletions src/import/chips/p9/procedures/hwp/io/p9_io_obus_pdwn_lanes.C
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Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,10 @@ fapi2::ReturnCode p9_io_obus_pdwn_lanes(const OBUS_TGT i_tgt, const uint32_t i_l
FAPI_IMP("p9_io_obus_pdwn_lanes: I/O Obus Entering");
const uint8_t GRP0 = 0;
const uint8_t LANES = 24;
const uint8_t TIMEOUT = 200;
const uint64_t DLY_1MS = 1000000;
const uint64_t DLY_1MIL_CYCLES = 1000000;

char l_tgtStr[fapi2::MAX_ECMD_STRING_LEN];
fapi2::toString(i_tgt, l_tgtStr, fapi2::MAX_ECMD_STRING_LEN);
FAPI_DBG("I/O Obus Pdwn Lanes %s, Lane Vector(0x%X)", l_tgtStr, i_lane_vector);
Expand All @@ -82,6 +86,33 @@ fapi2::ReturnCode p9_io_obus_pdwn_lanes(const OBUS_TGT i_tgt, const uint32_t i_l
{
if(((0x1 << lane) & i_lane_vector) != 0)
{
uint64_t l_data = 0;

// set rx_recal_abort = 1
FAPI_TRY(io::rmw(OPT_RX_RECAL_ABORT, i_tgt, GRP0, lane, 0x1),
"Error setting OPT_RX_RECAL_ABORT");

// poll for rx_lane_busy = 0
for (uint8_t l_count = 0; l_count < TIMEOUT; ++l_count)
{
FAPI_TRY(io::read(OPT_RX_LANE_BUSY, i_tgt, GRP0, lane, l_data),
"Error reading OPT_RX_LANE_BUSY");

if (io::get(OPT_RX_LANE_BUSY, l_data) == 0)
{
break;
}

FAPI_TRY(fapi2::delay(DLY_1MS, DLY_1MIL_CYCLES));
}

FAPI_ASSERT((io::get(OPT_RX_LANE_BUSY, l_data) == 0),
fapi2::IO_OBUS_PDWN_BAD_LANE_TIMEOUT()
.set_TARGET(i_tgt)
.set_GROUP(GRP0)
.set_LANE(lane),
"Timeout waiting for RX lane busy status");

FAPI_TRY(io::rmw(OPT_RX_LANE_ANA_PDWN, i_tgt, GRP0, lane, 0x01));
FAPI_TRY(io::rmw(OPT_RX_LANE_DIG_PDWN, i_tgt, GRP0, lane, 0x01));
FAPI_TRY(io::rmw(OPT_TX_LANE_PDWN , i_tgt, GRP0, lane, 0x01));
Expand Down
16 changes: 5 additions & 11 deletions src/import/chips/p9/procedures/hwp/io/p9_io_obus_scominit.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -54,13 +54,7 @@
#include <p9_obus_scom.H>
#include <p9_io_obus_scominit.H>
#include <p9_obus_scom_addresses.H>

//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
const uint64_t FIR_ACTION0 = 0x0000000000000000ULL;
const uint64_t FIR_ACTION1 = 0x2000000000000000ULL;
const uint64_t FIR_MASK = 0xDFFFFFFFFFFFC000ULL;
#include <p9_obus_fir_utils.H>

//------------------------------------------------------------------------------
// Function definitions
Expand Down Expand Up @@ -98,15 +92,15 @@ fapi2::ReturnCode p9_io_obus_scominit( const fapi2::Target<fapi2::TARGET_TYPE_OB
{
FAPI_TRY(fapi2::putScom(i_target,
OBUS_FIR_ACTION0_REG,
FIR_ACTION0),
OBUS_PHY_FIR_ACTION0),
"Error from putScom (OBUS_FIR_ACTION0_REG)");
FAPI_TRY(fapi2::putScom(i_target,
OBUS_FIR_ACTION1_REG,
FIR_ACTION1),
OBUS_PHY_FIR_ACTION1),
"Error from putScom (OBUS_FIR_ACTION1_REG)");
FAPI_TRY(fapi2::putScom(i_target,
OBUS_FIR_MASK_REG,
FIR_MASK),
OBUS_PHY_FIR_MASK),
"Error from putScom (OBUS_FIR_MASK_REG)");
}

Expand Down
6 changes: 1 addition & 5 deletions src/import/chips/p9/procedures/hwp/io/p9_io_obus_scominit.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -44,10 +44,6 @@
//------------------------------------------------------------------------------
#include <fapi2.H>

//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Structure definitions
//------------------------------------------------------------------------------
Expand Down
3 changes: 2 additions & 1 deletion src/import/chips/p9/procedures/hwp/io/p9_io_obus_scominit.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2015,2016
# Contributors Listed Below - COPYRIGHT 2015,2018
# [+] International Business Machines Corp.
#
#
Expand All @@ -24,4 +24,5 @@
# IBM_PROLOG_END_TAG

PROCEDURE=p9_io_obus_scominit
$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/nest)
$(call BUILD_PROCEDURE)
14 changes: 14 additions & 0 deletions src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,9 @@
#define OPT_TX_FIR_ERROR_INJECT_PL 0x800434000000003f, 48, 16 // register -- description
#define OPT_TX_BIT_MODE1_E_PL 0x80043c000000003f, 48, 16 // register -- description
#define OPT_TX_BIT_MODE2_E_PL 0x800444000000003f, 48, 16 // register -- description
*/
#define OPT_TX_IORESET 0x80044c000000003f, 48, 1 // reset the given tx lane
/*
#define OPT_TX_CNTL2_O_PL 0x80044c000000003f, 48, 16 // register -- description
#define OPT_TX_TDR_ENABLE 0x800454000000003f, 48, 1 // enable tdr on the given tx lane\r\n\tgap
#define OPT_TX_CNTL3_EO_PL 0x800454000000003f, 48, 16 // register -- description
Expand Down Expand Up @@ -525,13 +527,15 @@
#define OPT_RX_DAC_CNTL3_EO_PL 0x800018000000003f, 48, 16 // register -- description
#define OPT_RX_A_OFFSET_O0 0x800020000000003f, 48, 7 // this is the vertical offset of the odd low threshold sampling latch.
#define OPT_RX_A_OFFSET_O1 0x800020000000003f, 56, 7 // this is the vertical offset of the odd high threshold sampling latch.
*/
#define OPT_RX_DAC_CNTL4_EO_PL 0x800020000000003f, 48, 16 // register -- description
#define OPT_RX_A_INTEG_COARSE_GAIN 0x800028000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments.
#define OPT_RX_A_EVEN_INTEG_FINE_GAIN 0x800028000000003f, 52, 5 // this is integrator gain control used in making common mode adjustments.
#define OPT_RX_A_ODD_INTEG_FINE_GAIN 0x800028000000003f, 57, 5 // this is integrator gain control used in making common mode adjustments.
#define OPT_RX_DAC_CNTL5_EO_PL 0x800028000000003f, 48, 16 // register -- description
#define OPT_RX_A_CTLE_COARSE 0x800030000000003f, 48, 5 // this is the ctle coarse peak value, only 4 bits currently used thinking future
#define OPT_RX_A_CTLE_GAIN 0x800030000000003f, 53, 4 // this is the ctle gain setting
/*
#define OPT_RX_DAC_CNTL6_EO_PL 0x800030000000003f, 48, 16 // register -- description
#define OPT_RX_A_H1E_VAL 0x800038000000003f, 48, 7 // dfe h1 value for even samplers
#define OPT_RX_A_H1O_VAL 0x800038000000003f, 56, 7 // dfe h1 value for odd samplers
Expand All @@ -547,13 +551,15 @@
#define OPT_RX_DAC_CNTL2_O_PL 0x800088000000003f, 48, 16 // register -- description
#define OPT_RX_B_OFFSET_O0 0x800090000000003f, 48, 7 // this is the vertical offset of the odd low threshold sampling latch. the step size is vio/256.
#define OPT_RX_B_OFFSET_O1 0x800090000000003f, 56, 7 // this is the vertical offset of the odd high threshold sampling latch. the step size is vio/256.
*/
#define OPT_RX_DAC_CNTL3_O_PL 0x800090000000003f, 48, 16 // register -- description
#define OPT_RX_B_INTEG_COARSE_GAIN 0x800098000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments.
#define OPT_RX_B_EVEN_INTEG_FINE_GAIN 0x800098000000003f, 52, 5 // this is integrator gain control used in making common mode adjustments
#define OPT_RX_B_ODD_INTEG_FINE_GAIN 0x800098000000003f, 57, 5 // this is integrator gain control used in making common mode adjustments.
#define OPT_RX_DAC_CNTL4_O_PL 0x800098000000003f, 48, 16 // register -- description
#define OPT_RX_B_CTLE_COARSE 0x8000a0000000003f, 48, 5 // this is the ctle coarse peak value
#define OPT_RX_B_CTLE_GAIN 0x8000a0000000003f, 53, 4 // this is the ctle gain setting
/*
#define OPT_RX_DAC_CNTL5_O_PL 0x8000a0000000003f, 48, 16 // register -- description
#define OPT_RX_B_H1E_VAL 0x8000a8000000003f, 48, 7 // dfe h1 value for even samplers
#define OPT_RX_B_H1O_VAL 0x8000a8000000003f, 56, 7 // dfe h1 value for odd samplers
Expand All @@ -562,13 +568,15 @@
#define OPT_RX_DAC_CNTL7_O_PL 0x8000b0000000003f, 48, 16 // register -- description
#define OPT_RX_E_OFFSET_E 0x8000b8000000003f, 48, 7 // this is the vertical offset of the even low threshold sampling latch. the step size is vio/256.
#define OPT_RX_E_OFFSET_O 0x8000b8000000003f, 56, 7 // this is the vertical offset of the odd low threshold sampling latch. the step size is vio/256.
*/
#define OPT_RX_DAC_CNTL8_O_PL 0x8000b8000000003f, 48, 16 // register -- description
#define OPT_RX_E_INTEG_COARSE_GAIN 0x8000c0000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments.
#define OPT_RX_E_EVEN_INTEG_FINE_GAIN 0x8000c0000000003f, 52, 5 // this is integrator gain control used in making common mode adjustments
#define OPT_RX_E_ODD_INTEG_FINE_GAIN 0x8000c0000000003f, 57, 5 // this is integrator gain control used in making common mode adjustments.
#define OPT_RX_DAC_CNTL9_O_PL 0x8000c0000000003f, 48, 16 // register -- description
#define OPT_RX_E_CTLE_COARSE 0x8000c8000000003f, 48, 5 // this is the ctle coarse peak value
#define OPT_RX_E_CTLE_GAIN 0x8000c8000000003f, 53, 4 // this is the ctle gain setting
/*
#define OPT_RX_DAC_CNTL10_O_PL 0x8000c8000000003f, 48, 16 // register -- description
#define OPT_RX_PL_SPARE_MODE_0 0x800200000000003f, 48, 1 // per-lane spare mode latch.
#define OPT_RX_PL_SPARE_MODE_1 0x800200000000003f, 49, 1 // per-lane spare mode latch.
Expand Down Expand Up @@ -653,8 +661,10 @@
#define OPT_RX_PR_TRACE_DDC_SM 0x800258000000003f, 49, 5 // determines when to stop the state machine for trace debug.
#define OPT_RX_PR_TRACE_WOBBLE_STOP 0x800258000000003f, 54, 1 // enables the trace debug wobble state to stop the state machines.
#define OPT_RX_PR_TRACE_WOBBLE_SM 0x800258000000003f, 55, 3 // determines when to stop the state machine for trace debug.
*/
#define OPT_RX_PR_RESET 0x800258000000003f, 62, 1 // set this to reset cdr logic. power and clocks must be enabled in the slice.
#define OPT_RX_IORESET 0x800258000000003f, 63, 1 // reset the given rx lane (except the cdr logic)
/*
#define OPT_RX_BIT_CNTL4_EO_PL 0x800258000000003f, 48, 16 // register -- description
#define OPT_RX_PR_BUMP_SL_1STEP 0x800260000000003f, 48, 1 // rx manual phase rotator shift right pulse\r\n\twriting this bit to a 1 adds one to the binary pr value. an increase in pr value has the effect of moving the c2 clocks to the samplat earlier in time relative to the data.\r\n\tthis is just the opposite of what you might think and is also opposite the definition of bump_right_half servo command.
#define OPT_RX_PR_BUMP_SR_1STEP 0x800260000000003f, 49, 1 // rx manual phase rotator shift left pulse\r\n\twriting this bit to a 1 subtracts one from the binary pr value. a decrease in pr value has the effect of moving the c2 clocks to the samplat later in time relative to the data.\r\n\tthis is just the opposite of what you might think and is also opposite the definition of bump_left_half servo command.
Expand Down Expand Up @@ -685,7 +695,9 @@
#define OPT_RX_PR_RIGHT_EDGE_B 0x800318000000003f, 54, 6 // rx phase rotator b bank right edge
#define OPT_RX_B_PR_DFE_CLKADJ 0x800318000000003f, 60, 4 // tweak value in phase rotator steps for the bank b clock offset when doing dfe calibration
#define OPT_RX_BIT_STAT1_O_PL 0x800318000000003f, 48, 16 // register -- description
*/
#define OPT_RX_RUN_LANE 0x800320000000003f, 48, 1 // run training and subsequent recalibration on given lane
/*
#define OPT_RX_RUN_DCCAL 0x800320000000003f, 49, 1 // run on-die dc training on given lane
#define OPT_RX_RECAL_REQ 0x800320000000003f, 50, 1 // request recalibration on given lane
*/
Expand Down Expand Up @@ -934,7 +946,9 @@
#define OPT_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL 0x800970000000003f, 48, 1 // rx recalibration first latch offset adjustment enable with ctle-based disable
#define OPT_RX_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL 0x800970000000003f, 49, 1 // rx recalibratoin second latch offset adjustment enable with ctle-based disable
#define OPT_RX_RC_ENABLE_VGA_AMAX_MODE 0x800970000000003f, 50, 1 // rx recalibration vga ap measurement mode \r\n\t0: apx111 - anx000 mode \r\n\t1: 2ap-amin mode
*/
#define OPT_RX_RC_ENABLE_AUTO_RECAL 0x800970000000003f, 51, 1 // rx recalibration vga ap measurement mode \r\n\t0: apx111 - anx000 mode \r\n\t1: 2ap-amin mode
/*
#define OPT_RX_CTL_MODE27_EO_PG 0x800970000000003f, 48, 16 // register -- description
#define OPT_RX_DC_STEP_CNTL_OPT_ALIAS 0x800978000000003f, 48, 5 // rx dc step control opt alias
#define OPT_RX_DC_ENABLE_CM_COARSE_CAL 0x800978000000003f, 48, 1 // rx dc cal eye optimization common mode coarse calibration enable
Expand Down

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