Skip to content

Commit

Permalink
Generalize byte reading from SPD reading, for exp i2c reuse
Browse files Browse the repository at this point in the history 
Change-Id: I388e5abd6639464514fb9ca2d555362e431b753c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63209
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63538
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
  • Loading branch information
@aamarin @dcrowell77
aamarin authored and dcrowell77 committed Aug 6, 2018
1 parent 95b925b commit 6a03e83
Show file tree
Hide file tree
Showing 16 changed files with 764 additions and 517 deletions.
25 changes: 15 additions & 10 deletions src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -937,6 +937,7 @@ fapi_try_exit:
///
fapi2::ReturnCode eff_dimm::primary_stack_type()
{
constexpr size_t BYTE = 6;
uint8_t l_stack_type = 0;
uint8_t l_package_type = 0;

Expand All @@ -952,22 +953,26 @@ fapi2::ReturnCode eff_dimm::primary_stack_type()
// JEDEC standard says if the SPD says monolithic in A[7],
// stack type must be 00 or "SDP" which is what our enum is set to
FAPI_ASSERT( (l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_SDP),
fapi2::MSS_BAD_SPD()
.set_VALUE(l_stack_type)
.set_BYTE(6)
.set_DIMM_TARGET(iv_dimm),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE");
fapi2::MSS_FAILED_DATA_INTEGRITY_CHECK().
set_VALUE(l_stack_type).
set_BYTE(BYTE).
set_TARGET(iv_dimm).
set_FFDC_CODE(PRIMARY_STACK_TYPE),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE for %s",
mss::c_str(iv_dimm) );

break;

case mss::spd::NON_MONOLITHIC:
FAPI_ASSERT( (l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_DDP_QDP) ||
(l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_3DS),
fapi2::MSS_BAD_SPD()
.set_VALUE(l_stack_type)
.set_BYTE(6)
.set_DIMM_TARGET(iv_dimm),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE");
fapi2::MSS_FAILED_DATA_INTEGRITY_CHECK().
set_VALUE(l_stack_type).
set_BYTE(BYTE).
set_TARGET(iv_dimm).
set_FFDC_CODE(PRIMARY_STACK_TYPE),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE for %s",
mss::c_str(iv_dimm) );
break;

default:
Expand Down
3 changes: 3 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,9 @@ enum ffdc_function_codes
FREQ_SCOREBOARD_MAX_SUPPORTED_FREQ = 113,
FREQ_SCOREBOARD_SUPPORTED_FREQS = 114,
LIMIT_FREQ_BY_VPD = 115,

// eff_dimm.C
PRIMARY_STACK_TYPE = 116,
};

enum states
Expand Down
24 changes: 24 additions & 0 deletions src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -141,4 +141,28 @@
</callout>
</hwpError>


<hwpError>
<rc>RC_MSS_FAILED_DATA_INTEGRITY_CHECK</rc>
<description>
Bad data received.
Settings are incorrect for received data.
This could be code problem (decoding) or bad data.
</description>
<ffdc>VALUE</ffdc>
<ffdc>BYTE</ffdc>
<ffdc>FFDC_CODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>MEDIUM</priority>
</callout>
<callout>
<target>TARGET</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
<target>TARGET</target>
</deconfigure>
</hwpError>

</hwpErrors>
22 changes: 0 additions & 22 deletions src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,28 +96,6 @@
</deconfigure>
</hwpError>

<hwpError>
<rc>RC_MSS_BAD_SPD</rc>
<description>
Bad SPD data received.
Settings are incorrect within SPD.
This could be code problem (decoding) or bad SPD
</description>
<ffdc>VALUE</ffdc>
<ffdc>BYTE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>MEDIUM</priority>
</callout>
<callout>
<target>DIMM_TARGET</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
<target>DIMM_TARGET</target>
</deconfigure>
</hwpError>

<hwpError>
<rc>RC_MSS_INVALID_DRAM_GEN</rc>
<description>
Expand Down
65 changes: 35 additions & 30 deletions src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,9 @@
#include <generic/memory/lib/spd/common/dimm_module_decoder.H>
#include <generic/memory/lib/spd/common/rcw_settings.H>
#include <generic/memory/lib/spd/common/spd_decoder_base.H>
#include <generic/memory/lib/utils/mss_generic_check.H>
#include <generic/memory/lib/spd/spd_checker.H>
#include <generic/memory/lib/utils/mss_buffer_utils.H>

namespace mss
{
Expand Down Expand Up @@ -155,11 +157,12 @@ static fapi2::ReturnCode nibble_map_helper( const fapi2::Target<fapi2::TARGET_TY
const bool VALID_LOWER_NIBBLE = (i_bit_order >= LOW_BIT_ORDER_MIN) && (i_bit_order <= LOW_BIT_ORDER_MAX);
const bool VALID_UPPER_NIBBLE = (i_bit_order >= UP_BIT_ORDER_MIN) && (i_bit_order <= UP_BIT_ORDER_MAX);

FAPI_TRY(check::fail_for_invalid_value(i_target,
(VALID_LOWER_NIBBLE || VALID_UPPER_NIBBLE),
i_byte,
i_bit_order,
"Failed check on the NIBBLE_MAP field") );
FAPI_TRY(mss::check::invalid_value(i_target,
(VALID_LOWER_NIBBLE || VALID_UPPER_NIBBLE),
i_byte,
i_bit_order,
mss::BAD_SPD_DATA,
"Failed check on the NIBBLE_MAP field") );
fapi_try_exit:
return fapi2::current_err;
}
Expand All @@ -177,11 +180,12 @@ static fapi2::ReturnCode package_rank_map_helper( const fapi2::Target<fapi2::TAR
{
// Taken from the SPD JEDEC spec, only valid encoding, the rest are reserved
constexpr uint64_t VALID_VALUE = 0;
FAPI_TRY(check::fail_for_invalid_value(i_target,
(i_pkg_rank_map == VALID_VALUE),
i_byte,
i_pkg_rank_map,
"Failed check on Package Rank Map") );
FAPI_TRY(mss::check::invalid_value(i_target,
(i_pkg_rank_map == VALID_VALUE),
i_byte,
i_pkg_rank_map,
mss::BAD_SPD_DATA,
"Failed check on Package Rank Map") );
fapi_try_exit:
return fapi2::current_err;
}
Expand Down Expand Up @@ -486,7 +490,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_twrmin_msn, l_twrmin_lsb);
right_aligned_insert(l_buffer, l_twrmin_msn, l_twrmin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWRMIN));
Expand Down Expand Up @@ -519,7 +523,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_twtr_lmin_msn, l_twtr_lmin_lsb);
right_aligned_insert(l_buffer, l_twtr_lmin_msn, l_twtr_lmin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWTR_L_MIN));
Expand Down Expand Up @@ -553,7 +557,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_twtr_smin_msn, l_twtr_smin_lsb);
right_aligned_insert(l_buffer, l_twtr_smin_msn, l_twtr_smin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWTR_S_MIN));
Expand Down Expand Up @@ -1182,17 +1186,18 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
// Buffers used for bit manipulation
// Combine Bytes to create bitmap - right aligned
fapi2::buffer<uint64_t> l_buffer;
rightAlignedInsert(l_buffer, l_fourth_raw_byte, l_third_raw_byte, l_sec_raw_byte, l_first_raw_byte);
right_aligned_insert(l_buffer, l_fourth_raw_byte, l_third_raw_byte, l_sec_raw_byte, l_first_raw_byte);

// According to the JEDEC spec:
// Byte 22 (Bits 7~0) and Byte 23 are reserved and thus not supported
// Check for a valid value
constexpr size_t MAX_VALID_VAL = 0x3FFFF;
FAPI_TRY( check::fail_for_invalid_value(iv_target,
l_buffer <= MAX_VALID_VAL,
23,
l_buffer,
"Failed check on CAS latencies supported") );
FAPI_TRY( mss::check::invalid_value(iv_target,
l_buffer <= MAX_VALID_VAL,
23,
l_buffer,
mss::BAD_SPD_DATA,
"Failed check on CAS latencies supported") );

// Update output value only if range check passes
o_value = int64_t(l_buffer);
Expand Down Expand Up @@ -1259,7 +1264,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_tRASmin_msn, l_tRASmin_lsb);
right_aligned_insert(l_buffer, l_tRASmin_msn, l_tRASmin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TRASMIN));
Expand Down Expand Up @@ -1289,7 +1294,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_trcmin_msn, l_trcmin_lsb);
right_aligned_insert(l_buffer, l_trcmin_msn, l_trcmin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TRCMIN));
Expand Down Expand Up @@ -1320,7 +1325,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_trfc1min_msb, l_trfc1min_lsb);
right_aligned_insert(l_buffer, l_trfc1min_msb, l_trfc1min_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC1MIN));
Expand Down Expand Up @@ -1350,7 +1355,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_trfc2min_msb, l_trfc2min_lsb);
right_aligned_insert(l_buffer, l_trfc2min_msb, l_trfc2min_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC2MIN));
Expand Down Expand Up @@ -1380,7 +1385,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_trfc4min_msb, l_trfc4min_lsb);
right_aligned_insert(l_buffer, l_trfc4min_msb, l_trfc4min_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC4MIN));
Expand Down Expand Up @@ -1410,7 +1415,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<int64_t> l_buffer;
rightAlignedInsert(l_buffer, l_tfawmin_msn, l_tfawmin_lsb);
right_aligned_insert(l_buffer, l_tfawmin_msn, l_tfawmin_lsb);

// Update output only after check passes
FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TFAWMIN));
Expand Down Expand Up @@ -1689,7 +1694,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
{
// Combining bits to create timing value (in a buffer)
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_crc_msb, l_crc_lsb);
right_aligned_insert(l_buffer, l_crc_msb, l_crc_lsb);

// This value isn't bounded in the SPD document
o_value = l_buffer;
Expand Down Expand Up @@ -1718,7 +1723,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_last_nonzero_byte, l_cont_codes);
right_aligned_insert(l_buffer, l_last_nonzero_byte, l_cont_codes);

o_value = l_buffer;

Expand Down Expand Up @@ -1758,7 +1763,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_date_msb, l_date_lsb);
right_aligned_insert(l_buffer, l_date_msb, l_date_lsb);

o_value = l_buffer;

Expand Down Expand Up @@ -1790,7 +1795,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<uint32_t> l_buffer;
rightAlignedInsert(l_buffer, l_sn_byte_3, l_sn_byte_2, l_sn_byte_1, l_sn_byte_0);
right_aligned_insert(l_buffer, l_sn_byte_3, l_sn_byte_2, l_sn_byte_1, l_sn_byte_0);

o_value = l_buffer;

Expand Down Expand Up @@ -1831,7 +1836,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder

{
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_mfgid_msb, l_mfgid_lsb);
right_aligned_insert(l_buffer, l_mfgid_msb, l_mfgid_lsb);

o_value = l_buffer;

Expand Down
3 changes: 2 additions & 1 deletion src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@
#include <generic/memory/lib/spd/spd_decoder_def.H>
#include <generic/memory/lib/spd/common/dimm_module_decoder.H>
#include <generic/memory/lib/spd/spd_reader.H>
#include <generic/memory/lib/utils/mss_buffer_utils.H>

namespace mss
{
Expand Down Expand Up @@ -317,7 +318,7 @@ class decoder<DDR4, LRDIMM_MODULE, R > : public dimm_module_decoder

{
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_last_nonzero_byte, l_cont_codes);
right_aligned_insert(l_buffer, l_last_nonzero_byte, l_cont_codes);

o_output = l_buffer;

Expand Down
3 changes: 2 additions & 1 deletion src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@
#include <generic/memory/lib/spd/spd_decoder_def.H>
#include <generic/memory/lib/spd/spd_traits_ddr4.H>
#include <generic/memory/lib/spd/spd_reader.H>
#include <generic/memory/lib/utils/mss_buffer_utils.H>

namespace mss
{
Expand Down Expand Up @@ -285,7 +286,7 @@ class decoder<DDR4, RDIMM_MODULE, R > : public dimm_module_decoder

{
fapi2::buffer<uint16_t> l_buffer;
rightAlignedInsert(l_buffer, l_last_nonzero_byte, l_cont_codes);
right_aligned_insert(l_buffer, l_last_nonzero_byte, l_cont_codes);

o_output = l_buffer;

Expand Down
35 changes: 1 addition & 34 deletions src/import/generic/memory/lib/spd/spd_checker.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@

#include <fapi2.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <generic/memory/lib/utils/c_str.H>

namespace mss
{
Expand Down Expand Up @@ -123,40 +124,6 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Checks conditional passes and implements traces & exits if it fails
/// @tparam T input data of any size
/// @param[in] i_target fapi2 dimm target
/// @param[in] i_conditional conditional that we are testing against
/// @param[in] i_spd_byte_index current SPD byte
/// @param[in] i_spd_data debug data
/// @param[in] i_err_str error string to print out when conditional fails
/// @return FAPI2_RC_SUCCESS iff okay
///
template< typename T >
inline fapi2::ReturnCode fail_for_invalid_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const bool i_conditional,
const size_t i_spd_byte_index,
const T i_spd_data,
const char* i_err_str = "")
{
FAPI_ASSERT(i_conditional,
fapi2::MSS_BAD_SPD().
set_VALUE(i_spd_data).
set_BYTE(i_spd_byte_index).
set_DIMM_TARGET(i_target),
"%s %s Byte %d, data 0x%02x, extracted value: 0x%02x.",
spd::c_str(i_target),
i_err_str,
i_spd_byte_index,
i_spd_data);

return fapi2::FAPI2_RC_SUCCESS;
fapi_try_exit:
return fapi2::current_err;

} // fail_for_invalid_value

///
/// @brief Helper function to test if a DRAM generation is valid
/// @param[in] i_dram_gen the DRAM gen from SPD
Expand Down

0 comments on commit 6a03e83

Please sign in to comment.