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Moves CAS latency algorithm to generic folder
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Change-Id: Ie2a7e7f7b1f1e0f78716d458531715016a539ec0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65187
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65210
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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sglancy6 authored and crgeddes committed Sep 7, 2018
1 parent 3060376 commit 6a6d637
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Showing 12 changed files with 1,036 additions and 1,075 deletions.
504 changes: 0 additions & 504 deletions src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C

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399 changes: 0 additions & 399 deletions src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H

This file was deleted.

3 changes: 2 additions & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C
Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,14 @@
#include <algorithm>
#include <vector>
#include <map>
#include <mss.H>
#include <lib/freq/sync.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/utils/assert_noexit.H>
#include <generic/memory/lib/utils/count_dimm.H>
#include <generic/memory/lib/spd/spd_facade.H>
#include <generic/memory/lib/spd/spd_utils.H>
#include <generic/memory/lib/utils/conversions.H>
#include <lib/mss_attribute_accessors.H>

using fapi2::TARGET_TYPE_DIMM;
using fapi2::TARGET_TYPE_MCS;
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Expand Up @@ -191,7 +191,6 @@ enum ffdc_function_codes
GET_STARTING_WR_DQ_DELAY_VALUE = 95,

SUPPORTED_FREQS = 99,
SELECT_SUPPORTED_FREQ = 100,

// WR VREF functions
DRAM_TO_RP_REG = 101,
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4 changes: 2 additions & 2 deletions src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C
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Expand Up @@ -46,7 +46,7 @@

// mss lib
#include <generic/memory/lib/spd/spd_facade.H>
#include <lib/freq/cas_latency.H>
#include <generic/memory/lib/utils/freq/cas_latency.H>
#include <lib/freq/sync.H>
#include <lib/workarounds/freq_workarounds.H>
#include <generic/memory/lib/utils/c_str.H>
Expand Down Expand Up @@ -128,7 +128,7 @@ extern "C"
FAPI_TRY( get_spd_decoder_list(l_mca, l_spd_facades) );

// Instantiation of class that calculates CL algorithm
mss::cas_latency l_cas_latency( l_mca, l_spd_facades, l_supported_freqs, l_rc );
mss::cas_latency<mss::mc_type::NIMBUS> l_cas_latency( l_mca, l_spd_facades, l_supported_freqs, l_rc );

FAPI_TRY( l_rc, "%s. Failed to initialize cas_latency ctor", mss::c_str(l_mca) );

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142 changes: 0 additions & 142 deletions src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
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Expand Up @@ -54,127 +54,6 @@
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_INVALID_TIMING_VALUE</rc>
<description>Invalid value calculated for timing value based on MTB and FTB from SPD.</description>
<ffdc>VALUE</ffdc>
<ffdc>FUNCTION</ffdc>
<callout>
<target>DIMM_TARGET</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
<target>DIMM_TARGET</target>
</deconfigure>
<gard>
<target>DIMM_TARGET</target>
</gard>
</hwpError>

<hwpError>
<rc>RC_MSS_INVALID_CALCULATED_TCK</rc>
<description>
Invalid value clock period (less than equal 0).
Should be code bug and error comparing MRW and VPD SUPPRTED_FREQS
Caused by bad MRW values for MSS_MRW_SUPPORTED_FREQ
</description>
<ffdc>TAAMIN</ffdc>
<ffdc>PROPOSED_TCK</ffdc>
<ffdc>IS_3DS</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
<callout>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
<priority>MEDIUM</priority>
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc>
<description>
Current Configuration has no common supported CL values.
Caused by bad SPD on one of the plugged DIMMS
or DIMM configuration is not supported
</description>
<ffdc>CL_SUPPORTED</ffdc>
<callout>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
<priority>HIGH</priority>
</callout>
<deconfigure>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
</deconfigure>
<gard>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
</gard>
</hwpError>

<hwpError>
<rc>RC_MSS_FAILED_TO_FIND_SUPPORTED_CL</rc>
<description>
Desired CAS latency isn't supported in the common CAS latency bin retrieved from SPD.
</description>
<ffdc>DESIRED_CAS_LATENCY</ffdc>
<ffdc>COMMON_CLS</ffdc>
<ffdc>TAA</ffdc>
<ffdc>TCK</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
<callout>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
<priority>MEDIUM</priority>
</callout>
<deconfigure>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
</deconfigure>
<gard>
<childTargets>
<parent>MCA_TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
</gard>
</hwpError>

<hwpError>
<rc>RC_MSS_CL_EXCEEDS_TAA_MAX</rc>
<description>
Calculated Cas Latency exceeds JEDEC value for TAA Max
desired (and DIMM supported) cas_latency * proposed tck from mss freq attributes > jedec taa_max
Probably due to MRW/ VPD freqs being too high
</description>
<ffdc>CAS_LATENCY</ffdc>
<ffdc>TCK</ffdc>
<ffdc>TAA_MAX</ffdc>
<ffdc>COMPARE</ffdc>
<ffdc>IS_3DS</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_FREQ_NOT_EQUAL_NEST_FREQ</rc>
<description>
Expand Down Expand Up @@ -471,27 +350,6 @@
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_SELECTED_FREQ_NOT_SUPPORTED</rc>
<description>Selected freq based on calculations from the DIMM and VPD is not supported</description>
<ffdc>SUPPORTED_FREQ_0</ffdc>
<ffdc>SUPPORTED_FREQ_1</ffdc>
<ffdc>SUPPORTED_FREQ_2</ffdc>
<ffdc>SUPPORTED_FREQ_3</ffdc>
<ffdc>FREQ</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
<callout>
<childTargets>
<parent>TARGET</parent>
<childType>TARGET_TYPE_DIMM</childType>
</childTargets>
<priority>MEDIUM</priority>
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_FREQ_TO_NEST_FREQ_RATIO_TOO_LARGE</rc>
<description>
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Original file line number Diff line number Diff line change
Expand Up @@ -53,23 +53,6 @@
</deconfigure>
</hwpError>

<hwpError>
<rc>RC_MSS_EMPTY_VECTOR</rc>
<description>
Empty vector conditional failed.
</description>
<ffdc>RECEIVED</ffdc>
<ffdc>FUNCTION</ffdc>
<callout>
<target>TARGET</target>
<priority>MEDIUM</priority>
</callout>
<callout>
<procedure>CODE</procedure>
<priority>LOW</priority>
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_INVALID_RTT_WR_ENCODING</rc>
<description>
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64 changes: 64 additions & 0 deletions src/import/generic/memory/lib/utils/freq/cas_latency.C
Original file line number Diff line number Diff line change
@@ -0,0 +1,64 @@
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/generic/memory/lib/utils/freq/cas_latency.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */

///
/// @file cas_latency.C
/// @brief CAS latency class implementation
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP

// std lib
#include <limits.h>
#include <algorithm>

// fapi2
#include <fapi2.H>

// mss lib
#include <generic/memory/lib/utils/freq/cas_latency.H>

namespace mss
{

const std::vector< uint32_t > CasLatencyTraits<mc_type::NIMBUS>::SUPPORTED_FREQS =
{
DIMM_SPEED_1866,
DIMM_SPEED_2133,
DIMM_SPEED_2400,
DIMM_SPEED_2666,
};

const std::vector< uint32_t > CasLatencyTraits<mc_type::EXPLORER>::SUPPORTED_FREQS =
{
DIMM_SPEED_2666,
DIMM_SPEED_2933,
DIMM_SPEED_3200,
};

}// mss

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