Enable p9_pm_stop_gpe_init call in istep15

Previously commented out for axone, now supported.
Tested by unset EARLY_TESTCASES in simics_axone.config

Change-Id: If62ab5b2c87d115d0f9f3e1fa20496e9f18c122e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76047
Reviewed-by: Glenn Miles <milesg@ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/usr/isteps/istep15/host_start_stop_engine.C

@@ -79,11 +79,9 @@ void* host_start_stop_engine (void *io_pArgs)
         }
 #endif
 
-// Skip initializing the PM complex in axone simics for now
-#ifndef CONFIG_AXONE_BRING_UP
         //Use targeting code to get a list of all processors
         TARGETING::TargetHandleList l_procChips;
-        getAllChips( l_procChips, TARGETING::TYPE_PROC   );
+        getAllChips( l_procChips, TARGETING::TYPE_PROC );
 
         for (const auto & l_procChip: l_procChips)
         {
@@ -92,6 +90,10 @@ void* host_start_stop_engine (void *io_pArgs)
             fapi2::Target<TARGET_TYPE_PROC_CHIP>l_fapi2CpuTarget(
                                                               (l_procChip));
 
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                "Calling p9_pm_stop_gpe_init for 0x%.8X target",
+                TARGETING::get_huid(l_procChip) );
+
             //call p9_pm_stop_gpe_init.C HWP
             FAPI_INVOKE_HWP(l_errl,
                             p9_pm_stop_gpe_init,
@@ -105,7 +107,6 @@ void* host_start_stop_engine (void *io_pArgs)
                 TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_start_stop_engine:: failed on proc with HUID : %d",TARGETING::get_huid(l_procChip)  );
             }
         }
-#endif
 
 #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS
         // Starting SGPE in istep15.4 causes OIMR0 register to be improperly