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Add DDR4 RCD attributes from the EXP resp structure
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Change-Id: I6662bfd2f6dfa0e890be360e5f34b977ec4b333d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/92211
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/92245
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
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@aamarin @crgeddes
aamarin authored and crgeddes committed Mar 25, 2020
1 parent fde4c9f commit 80ecda0
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208 changes: 208 additions & 0 deletions src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
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Expand Up @@ -540,4 +540,212 @@
<mssAccessorName>disable_therm_init_read</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC00</id>
<targetType>TARGET_TYPE_OCMB_CHIP</targetType>
<description>
F0RC00: Global Features Control Word from the DDR4 RCD Spec.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc00</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC01</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC01: Clock Driver Enable Control Word from the DDR4 RCD Spec.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc01</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC03</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC03 - CA and CS Signals Driver Characteristics Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc03</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC04</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC04 - ODT and CKE Signals Driver Characteristics Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc04</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC05</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC05 - Clock Driver Characteristics Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc05</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC0B</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
Operating Voltage VDD and VrefCA Source Control Word from the DDR4 RCD Spec.
From the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc0b</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC0E</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC0E - Parity, NV Mode Enable, and ALERT Configuration Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc0e</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC0F</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC0F - Command Latency Adder Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc0f</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC1X</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC1x - Internal VrefCA Control Word from the DDR4 RCD Spec;
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc1x</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F0RC7X</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F0RC7x: IBT Control Word from the DDR4 RCD Spec;
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f0rc7x</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F1RC00</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F1RC00: Data Buffer Interface Driver Characteristics Control Word from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f1rc00</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F1RC02</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F1RC02 - CA and CS Output Slew Rate Control from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f1rc02</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F1RC03</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F1RC03 - ODT and CKEn Output Slew Rate Control from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f1rc03</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F1RC04</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F1RC04 - Clock Driver Output Slew Rate Control from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f1rc04</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MSS_EXP_RESP_DDR4_F1RC05</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
F1RC05 - Data Buffer Interface Output Slew Rate Control from the DDR4 RCD Spec.
From user_response_rc_msdg_t in draminit..
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<array>2</array>
<writeable/>
<mssAccessorName>exp_resp_ddr4_f1rc05</mssAccessorName>
</attribute>
</attributes>
18 changes: 18 additions & 0 deletions src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml
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Expand Up @@ -362,4 +362,22 @@
<mssAccessorName>therm_sensor_differential_i2c_addr</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MEM_EFF_SUPPORTED_RCD</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
ARRAY[DIMM]
Byte 264: Registered Clock Drivers (RCD).
DDIMM SPD spec.
Module’s supported RCD options
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<enum>NO_RCD = 0, RCD_PER_CHANNEL_1 = 1</enum>
<writeable/>
<array>2</array>
<mssUnits>bool</mssUnits>
<mssAccessorName>supported_rcd</mssAccessorName>
</attribute>

</attributes>

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