PM: Checks for PGPE/SGPE Region in PPMR/QPMR(4/4)

    4th commit in series of 4 commits which combined moves SGPE/PGPE
    SRAM regions, and also allows to do so easily in future.

    Commit 1(Hcode): Adds fields to OCC Complex Shared SRAM for storing SGPE
    and PGPE region addresses/size, image header and debug header.

    Commit 2(Hostboot): Moves around SGPE/PGPE regions, and adds fields
    to QPMR/PPMR for storing SGPE/PGPE region info

    Commit 3(Hcode): Populates the newly added SGPE/PGPE region info
    fields in QPMR/PPMR

    Commit 4(Hostboot): Adds check for QPMR and PPMR fields in the Hostboot Code

    Key_Cronus_Test=PM_REGRESS

HW-Image-Coreq: yes
HW-Image-Prereq: Id9493ba0843c26975e1b72e558501df7140fa10c
Change-Id: Ifa4a4acf9a202da7a0357747d57d5f26613bc3cd
CQ: SW447651
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67223
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67364
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C

@@ -1534,6 +1534,24 @@ fapi2::ReturnCode buildSgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip
         //updating local instance of QPMR header
         memcpy( &o_qpmrHdr, i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, sizeof(QpmrHeaderLayout_t));
 
+        FAPI_ASSERT( ( SWIZZLE_4_BYTE(o_qpmrHdr.sgpeSramRegionStart) == OCC_SRAM_SGPE_BASE_ADDR ),
+                     fapi2::QPMR_HDR_BUILD_FAILURE()
+                     .set_EC_LEVEL( i_procFuncModel.getChipLevel() )
+                     .set_CHIP_TYPE( i_procFuncModel.getChipName() )
+                     .set_MAX_ALLOWED_SIZE( rcTemp )
+                     .set_ACTUAL_SIZE( ppeSection.iv_size ),
+                     "QPMR SGPE Sram Region Start Mismatch Value=0x%x Expected=0x%x"
+                     ,o_qpmrHdr.sgpeSramRegionStart, OCC_SRAM_SGPE_BASE_ADDR);
+
+        FAPI_ASSERT( ( SWIZZLE_4_BYTE(o_qpmrHdr.sgpeSramRegionSize)  == OCC_SRAM_SGPE_REGION_SIZE ),
+                     fapi2::QPMR_HDR_BUILD_FAILURE()
+                     .set_EC_LEVEL( i_procFuncModel.getChipLevel() )
+                     .set_CHIP_TYPE( i_procFuncModel.getChipName() )
+                     .set_MAX_ALLOWED_SIZE( rcTemp )
+                     .set_ACTUAL_SIZE( ppeSection.iv_size ),
+                     "QPMR SGPE Sram Region Size Mismatch Value=0x%x Expected=0x%x"
+                     ,o_qpmrHdr.sgpeSramRegionSize, OCC_SRAM_SGPE_REGION_SIZE);
+
         FAPI_DBG("SGPE Boot Copier");
         rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l1BootLoader,
                                      pSgpeImg,
@@ -1950,6 +1968,26 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip
 
         memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t));
 
+
+        FAPI_ASSERT ( (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_region_start) == OCC_SRAM_PGPE_BASE_ADDR),
+                      fapi2::P9_XIP_SECTION_PGPE_PPMR()
+                     .set_EC_LEVEL( i_procFuncModel.getChipLevel() )
+                     .set_CHIP_TYPE( i_procFuncModel.getChipName() )
+                     .set_MAX_ALLOWED_SIZE( rcTemp )
+                     .set_ACTUAL_SIZE( ppeSection.iv_size ),
+                     "PPMR PGPE Sram Region Start mismatch. Value=0x%x Expected=0x%x",
+                      SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_region_start), OCC_SRAM_PGPE_BASE_ADDR );
+
+        FAPI_ASSERT ( (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_region_size) == OCC_SRAM_PGPE_REGION_SIZE),
+                      fapi2::P9_XIP_SECTION_PGPE_PPMR()
+                     .set_EC_LEVEL( i_procFuncModel.getChipLevel() )
+                     .set_CHIP_TYPE( i_procFuncModel.getChipName() )
+                     .set_MAX_ALLOWED_SIZE( rcTemp )
+                     .set_ACTUAL_SIZE( ppeSection.iv_size ),
+                     "PPMR PGPE Sram Region Size mismatch. Value=0x%x Expected=0x%x",
+                      SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_region_size), OCC_SRAM_PGPE_REGION_SIZE);
+
+
         rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader,
                                      pPgpeImg,
                                      P9_XIP_SECTION_PGPE_LVL1_BL,