Reinstates exp_draminit_mc with change_addr_mux_sel fix

Change-Id: Ief62fadce588bf65e249ae771bd03ab31ed4bddf
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71201
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71218
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C

@@ -22,3 +22,79 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file exp_mss_draminit_mc.C
+/// @brief Initialize the memory controller to take over the DRAM
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+
+#include <generic/memory/lib/utils/c_str.H>
+#include <generic/memory/lib/utils/find.H>
+#include <generic/memory/lib/utils/count_dimm.H>
+
+#include <lib/mc/exp_port.H>
+
+extern "C"
+{
+///
+/// @brief Initialize the MC now that DRAM is up
+/// @param[in] i_target, the MC of the ports
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+    fapi2::ReturnCode exp_draminit_mc( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target )
+    {
+
+        FAPI_INF("%s Start exp_draminit MC", mss::c_str(i_target));
+
+        //skip this ocmb_chip if we have no DIMM's configured
+        if(mss::count_dimm(i_target) == 0)
+        {
+            FAPI_INF("No DIMM's configured on %s. Skipping this OCMB_CHIP.", mss::c_str(i_target));
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        // Enable Power management based off of mrw_power_control_requested
+        FAPI_TRY( mss::enable_power_management(i_target), "%s Failed to enable power management",
+                  mss::c_str(i_target) );
+
+        // Set the IML Complete bit. Steve Powell to find a bit in the SRQ to use for this purpose
+        FAPI_TRY( mss::change_iml_complete(i_target, mss::HIGH), "%s Failed to set_ipm_complete",
+                  mss::c_str(i_target));
+
+        // Set DFI init start requested from Stephen Powell
+        FAPI_TRY( mss::change_dfi_init_start(i_target, mss::ON ), "%s Failed to change_dfi_init_start",
+                  mss::c_str(i_target));
+
+        // Re-enable port fails.
+        FAPI_TRY( mss::change_port_fail_disable(i_target, mss::OFF ),
+                  "%s Failed to change_port_fail_disable", mss::c_str(i_target) );
+
+        // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in
+        // MBAREF0Q should retain their initialization values.
+        FAPI_TRY( mss::change_refresh_enable(i_target, mss::HIGH), "%s Failed change_refresh_enable",
+                  mss::c_str(i_target) );
+
+        // Enable periodic short zq cal
+        FAPI_TRY( mss::enable_zq_cal(i_target), "%s Failed enable_zq_cal", mss::c_str(i_target) );
+
+        // Enable ecc checking
+        FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );
+
+        // Apply marks from OCMB VPD
+        FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );
+
+        // TODO: Move mss::unmask::after_draminit_mc to generic and call it
+        // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked.
+        //FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) );
+
+    fapi_try_exit:
+        FAPI_INF("%s End exp_draminit MC", mss::c_str(i_target));
+        return fapi2::current_err;
+    }
+}

src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.H

@@ -22,3 +22,33 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_draminit_mc.H
+/// @brief Initialize the memory controller to take over the DRAM
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#ifndef EXP_DRAMINIT_MC_H_
+#define EXP_DRAMINIT_MC_H_
+
+#include <fapi2.H>
+
+typedef fapi2::ReturnCode (*exp_draminit_mc_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&);
+
+extern "C"
+{
+
+    ///
+    /// @brief Trains the OCMB link
+    /// @param[in] i_target the OCMB target to operate on
+    /// @return FAPI2_RC_SUCCESS iff ok
+    ///
+    fapi2::ReturnCode exp_draminit_mc(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target);
+}
+
+#endif

src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.mk

@@ -22,3 +22,11 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
+
+
+
+-include 00exp_common.mk
+
+PROCEDURE=exp_draminit_mc
+$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE)))
+$(call BUILD_PROCEDURE)

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H

@@ -22,3 +22,114 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_port.H
+/// @brief Code to support ports
+///
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: HB:FSP
+
+#ifndef __MSS_EXP_PORT_H_
+#define __MSS_EXP_PORT_H_
+
+#include <fapi2.H>
+#include <explorer_scom_addresses.H>
+#include <explorer_scom_addresses_fld.H>
+#include <lib/exp_attribute_accessors_manual.H>
+#include <lib/shared/exp_consts.H>
+#include <generic/memory/lib/utils/mc/gen_mss_port.H>
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
+#include <mss_explorer_attribute_getters.H>
+
+namespace mss
+{
+
+///
+/// @brief ATTR_MSS_MEM_MVPD_FWMS getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>
+/// @param[out] uint32_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (G)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Mark store records from MPVD Lx
+/// keyword
+///
+template<>
+inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+                                   uint32_t (&o_array)[mss::MARK_STORE_COUNT])
+{
+    return mss::attr::get_mvpd_fwms(i_target, o_array);
+}
+
+///
+/// @class Traits and policy class for port code - specialization for Explorer. The target of registers is TARGET_TYPE_OCMB_CHIP
+///
+template<>
+class portTraits< mss::mc_type::EXPLORER >
+{
+    public:
+        // scom register definition
+        static constexpr uint64_t MBARPC0Q_REG = EXPLR_SRQ_MBARPC0Q;
+
+        static constexpr uint64_t FARB0Q_REG = EXPLR_SRQ_MBA_FARB0Q;
+        static constexpr uint64_t FARB5Q_REG = EXPLR_SRQ_MBA_FARB5Q;
+        static constexpr uint64_t FARB6Q_REG = EXPLR_SRQ_MBA_FARB6Q;
+        static constexpr uint64_t FARB9Q_REG = EXPLR_SRQ_MBA_FARB9Q;
+        static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q;
+        static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR;
+        static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q;
+        static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0;
+
+        static constexpr uint64_t RRQ_REG = EXPLR_SRQ_MBA_RRQ0Q;
+        static constexpr uint64_t WRQ_REG = EXPLR_SRQ_MBA_WRQ0Q;
+
+        static constexpr uint64_t MAGIC_NUMBER_SIM = 765;
+        static constexpr uint64_t MAGIC_NUMBER_NOT_SIM = 196605;
+
+        // scom register field definition
+        enum
+        {
+            CFG_MIN_MAX_DOMAINS_ENABLE = EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE,
+            CFG_CCS_INST_RESET_ENABLE = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE,
+            CFG_DDR_RESETN = EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN,
+            CFG_CCS_ADDR_MUX_SEL = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL,
+            //TODO: It's not defined in scom register header file. Change this once it's available in scom address header file
+            CFG_INIT_COMPLETE = 32, //EXPLR_SRQ_MBA_FARB6Q_CFG_INIT_COMPLETE,
+            CFG_ZQ_PER_CAL_ENABLE = EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE,
+
+            REFRESH_ENABLE = EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE,
+
+            ECC_CHECK_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT,
+            ECC_CORRECT_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT,
+            ECC_USE_ADDR_HASH = EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH,
+
+            PORT_FAIL_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE,
+            DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE,
+            RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY,
+
+            RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION,
+            RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION,
+            RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN,
+            DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY,
+            DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN,
+            DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY,
+            DSM0Q_WRDONE_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN,
+            FARB0Q_RCD_PROTECTION_TIME = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME,
+            FARB0Q_RCD_PROTECTION_TIME_LEN = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN,
+
+            FWMS0_MARK = EXPLR_RDF_FWMS0_MARK,
+            FWMS0_MARK_LEN = EXPLR_RDF_FWMS0_MARK_LEN,
+            FWMS0_EXIT_1 = EXPLR_RDF_FWMS0_EXIT_1,
+
+            RRQ_FIFO_MODE = EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE,
+            WRQ_FIFO_MODE = EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE,
+        };
+};
+
+
+}// mss
+
+#endif

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H

@@ -36,8 +36,13 @@
 #ifndef EXP_CONSTS_H
 #define EXP_CONSTS_H
 
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
+
 namespace mss
 {
+
+constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::EXPLORER;
+
 namespace exp
 {
 

src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C

@@ -72,7 +72,7 @@ constexpr uint64_t BIT_SPARE_7 = 15;        //       7: SPARE
 template<>
 fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
 {
-    typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+    typedef portTraits<mss::mc_type::NIMBUS> TT;
 
     uint32_t l_memcal_interval = 0;
     uint32_t l_zqcal_interval = 0;