Add row repair access functions and attr switches for p9c

Change-Id: I07d38475165278a4f0400ee8f5fc38bc5b7b7552 CQ:SW445411 Depends-On: I728a494f91f1f460c0700bbeeca47a0e5739622f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66599 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66667 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
open-power · Oct 5, 2018 · 93192af · 93192af
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commit 93192af
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diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C
@@ -4788,6 +4788,7 @@ fapi_try_exit:
 /// @param[in] i_delay delay associated with this instruction
 /// @param[in,out] io_instruction_number position in CCS program in which to insert MRS command (will be incremented)
 /// @return FAPI2_RC_SUCCESS iff successful
+/// @note MR should be selected using i_addr.bank with constants from dimmConsts.H
 fapi2::ReturnCode add_mrs_to_ccs_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
                                       const access_address i_addr,
                                       const uint32_t i_delay,

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.H
@@ -219,6 +219,7 @@ fapi2::ReturnCode setup_b_side_ccs(const fapi2::Target<fapi2::TARGET_TYPE_MBA>&
 /// @param[in] i_delay delay associated with this instruction
 /// @param[in,out] io_instruction_number position in CCS program in which to insert MRS command (will be incremented)
 /// @return FAPI2_RC_SUCCESS iff successful
+/// @note MR should be selected using i_addr.bank with constants from dimmConsts.H
 fapi2::ReturnCode add_mrs_to_ccs_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
                                       const access_address i_addr,
                                       const uint32_t i_delay,

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C
@@ -51,6 +51,7 @@
 #include <p9c_mss_funcs.H>
 #include <p9c_mss_unmask_errors.H>
 #include <p9c_mss_draminit_mc.H>
+#include <p9c_mss_row_repair.H>
 #include <generic/memory/lib/utils/c_str.H>
 #include <generic/memory/lib/utils/find.H>
 #include <dimmConsts.H>
@@ -92,6 +93,10 @@ extern "C" {
             FAPI_INF( "%s +++ Setting up adr inversion for port 1 +++", mss::c_str(i_target));
             FAPI_TRY(mss_enable_addr_inversion(l_mba), "---Error During ADR Inversion");
 
+            //Step Two.3: Apply row repairs on each MBA's DIMM
+            FAPI_INF( "%s +++ Applying sPPR row repairs +++", mss::c_str(i_target));
+            FAPI_TRY(p9c_mss_deploy_row_repairs(l_mba), "---Error During Row Reapirs");
+
             // Step Three: Enable Refresh
             FAPI_INF( "%s +++ Enabling Refresh +++", mss::c_str(i_target));
             FAPI_TRY(fapi2::getScom(l_mba, CEN_MBA_MBAREF0Q, l_mba01_ref0q_data_buffer_64));

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H
@@ -38,6 +38,7 @@
 #include <dimmConsts.H>
 
 /// @brief Struct to contain DRAM address bits
+/// @note For DDR4, bank should be set to {BA0, BA1, BG0, BG1}
 struct access_address
 {
     uint32_t row_addr;

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H
@@ -26,15 +26,36 @@
 #define __P9C_MSS_ROW_REPAIR__
 
 #include <fapi2.H>
+#include <dimmConsts.H>
 
 typedef fapi2::ReturnCode (*p9c_mss_row_repair_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
         const uint8_t  i_port,
         const uint8_t  i_mrank,
         const uint8_t  i_srank,
+        const uint8_t  i_bg,
         const uint8_t  i_bank,
         const uint32_t i_row,
         const uint32_t i_dram_bitmap);
 
+// These consts describe the organization of ATTR_ROW_REPAIR_DATA
+constexpr size_t ROW_REPAIR_BYTES_PER_RANK = 4;
+constexpr size_t DRAM_POS = 0;
+constexpr size_t DRAM_POS_LEN = 5;
+constexpr size_t SRANK = 5;
+constexpr size_t SRANK_LEN = 3;
+constexpr size_t BANK_GROUP = 8;
+constexpr size_t BANK_GROUP_LEN = 2;
+constexpr size_t BANK = 10;
+constexpr size_t BANK_LEN = 3;
+constexpr size_t ROW_ADDR = 13;
+constexpr size_t ROW_ADDR_LEN = 18;
+constexpr size_t REPAIR_VALID = 31;
+constexpr uint8_t MC_MAX_DRAMS_PER_RANK_X4 = MAX_DRAMS_PER_RANK_X4 + 1;
+
+// This is the value to shift the input DRAM position to the last 20 bits of l_write_pattern
+constexpr uint8_t DRAM_START_BIT = 44;
+constexpr uint8_t DRAM_LEN = 64 - DRAM_START_BIT;
+
 extern "C"
 {
 
@@ -43,6 +64,7 @@ extern "C"
     /// @param[in] i_port port for repair
     /// @param[in] i_mrank master rank of address to repair
     /// @param[in] i_srank slave rank of address to repair
+    /// @param[in] i_bg bank group bits of address to repair
     /// @param[in] i_bank bank bits of address to repair
     /// @param[in] i_row row bits of address to repair
     /// @param[in] i_dram_bitmap bitmap of DRAMs selected for repair (b'1 to repair, b'0 to not repair)
@@ -51,10 +73,60 @@ extern "C"
                                          const uint8_t  i_port,
                                          const uint8_t  i_mrank,
                                          const uint8_t  i_srank,
+                                         const uint8_t  i_bg,
                                          const uint8_t  i_bank,
                                          const uint32_t i_row,
                                          const uint32_t i_dram_bitmap);
 
+
+    /// @brief Deploy PPR row repairs, if supported, according to VPD attributes
+    /// @param[in] i_target_mba mba target
+    /// @return FAPI2_RC_SUCCESS iff successful
+    fapi2::ReturnCode p9c_mss_deploy_row_repairs(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba);
+
+    /// @brief Clear the corresponding bad_bits after a row repair operation
+    /// @param[in] i_dram_width the DRAM width
+    /// @param[in] i_dram the DRAM index
+    /// @param[in,out] io_bad_bits array bad bits data from VPD
+    /// @return FAPI2_RC_SUCCESS iff successful
+    fapi2::ReturnCode clear_bad_dq_for_row_repair(const uint8_t i_dram_width,
+            const uint8_t i_dram,
+            uint8_t (&io_bad_bits)[DIMM_DQ_RANK_BITMAP_SIZE]);
+
+    /// @brief Clear a row repair entry from the VPD data
+    /// @param[in] i_rank master rank
+    /// @param[in,out] io_row_repair_data data for this DIMM/rank from the VPD
+    /// @return FAPI2_RC_SUCCESS iff successful
+    fapi2::ReturnCode clear_row_repair_entry(const uint8_t i_rank,
+            uint8_t (&io_row_repair_data)[MAX_RANKS_PER_DIMM][ROW_REPAIR_BYTES_PER_RANK]);
+
+    /// @brief Decode a row repair entry from an encoded buffer
+    /// @param[in] i_repair row repair data buffer
+    /// @param[out] o_dram DRAM position
+    /// @param[out] o_srank slave rank
+    /// @param[out] o_bg bank group
+    /// @param[out] o_bank bank address
+    /// @param[out] o_row row address
+    /// @return true if the repair request is valid, false otherwise
+    bool valid_row_repair_entry( const fapi2::buffer<uint32_t> i_repair,
+                                 uint8_t& o_dram,
+                                 uint8_t& o_srank,
+                                 uint8_t& o_bg,
+                                 uint8_t& o_bank,
+                                 uint32_t& o_row );
+
+    /// @brief Build a table of PPR row repairs from attribute data for a given DIMM
+    /// @param[in] i_target DIMM target
+    /// @param[in] i_dram_width the DRAM width
+    /// @param[in] i_row_repair_data array of row repair attribute values for the DIMM
+    /// @param[out] o_repairs_per_dimm array of row repair data buffers
+    /// @param[in,out] io_dram_bad_in_ranks array of how many ranks in which each DRAM was found to need a repair
+    /// @return FAPI2_RC_SUCCESS iff successful
+    fapi2::ReturnCode build_row_repair_table(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+            const uint8_t i_dram_width,
+            const uint8_t i_row_repair_data[MAX_RANKS_PER_DIMM][ROW_REPAIR_BYTES_PER_RANK],
+            std::vector<fapi2::buffer<uint32_t>>& o_repairs_per_dimm,
+            uint8_t io_dram_bad_in_ranks[MC_MAX_DRAMS_PER_RANK_X4]);
 }
 
 #endif
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.mk b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.mk
@@ -28,4 +28,6 @@ PROCEDURE=p9c_mss_row_repair
 $(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE)))
 lib${PROCEDURE}_DEPLIBS+=p9c_mss_ddr4_funcs
 lib${PROCEDURE}_DEPLIBS+=p9c_mss_funcs
+lib${PROCEDURE}_DEPLIBS+=p9c_dimmBadDqBitmapFuncs
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_rowRepairFuncs
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml
@@ -378,6 +378,61 @@
   </callout>
 </hwpError>
 
+<hwpError>
+  <rc>RC_CEN_ROW_REPAIR_WITH_MNFG_REPAIRS_DISABLED</rc>
+  <description>Row repairs were requested but DRAM repairs are disabled in MNFG flags</description>
+  <ffdc>DIMM_TARGET</ffdc>
+  <ffdc>RANK</ffdc>
+  <callout>
+    <target>DIMM_TARGET</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>LOW</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_CEN_RANK_OUT_OF_BOUNDS</rc>
+  <description>Rank supplied to clear_row_repair_entry is out of bounds</description>
+  <ffdc>RANK</ffdc>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_CEN_DRAM_INDEX_OUT_OF_BOUNDS</rc>
+  <description>DRAM index supplied to clear_bad_dq_for_row_repair is out of bounds</description>
+  <ffdc>DRAM</ffdc>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_CEN_ROW_REPAIR_ENTRY_OUT_OF_BOUNDS</rc>
+  <description>VPD contained out of bounds row repair entry</description>
+  <ffdc>DIMM_TARGET</ffdc>
+  <ffdc>DRAM</ffdc>
+  <ffdc>MRANK</ffdc>
+  <ffdc>SRANK</ffdc>
+  <ffdc>BANK_GROUP</ffdc>
+  <ffdc>BANK</ffdc>
+  <ffdc>ROW</ffdc>
+  <callout>
+    <target>DIMM_TARGET</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>LOW</priority>
+  </callout>
+</hwpError>
+
 
 <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID -->
 </hwpErrors>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml b/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2018                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -58,6 +58,7 @@
     <enum>
         MNFG_NO_FLAG                        = 0x0000000000000000,
         MNFG_THRESHOLDS                     = 0x0000000000000001,
+        MNFG_TEST_ALL_SPARE_DRAM_ROWS       = 0x0000000000000040,
         MNFG_DISABLE_DRAM_REPAIRS           = 0x0000000000000080,
         MNFG_ENABLE_STANDARD_PATTERN_TEST   = 0x0000000000000200,
         MNFG_DISABLE_FABRIC_eREPAIR         = 0x0000000000000800,