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Adds MCBIST functional verification tests
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Change-Id: I122de19702ea9a7e30534d752925c1498012bf2f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90791
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90815
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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sglancy6 authored and dcrowell77 committed Feb 13, 2020
1 parent c526308 commit 97fc552
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Showing 3 changed files with 114 additions and 1 deletion.
5 changes: 5 additions & 0 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H
View file
Expand Up @@ -294,6 +294,10 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>

enum
{
// The start/end address config registers have common lengths and bits, just including 1 below
MCB_ADDR_CONFIG = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0,
MCB_ADDR_CONFIG_LEN = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN,

// Subtest control bits. These are the same in all '16 bit subtest' field
COMPL_1ST_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD,
COMPL_2ND_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD,
Expand Down Expand Up @@ -557,6 +561,7 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>
//MCBIST FIR mask
MCB_PROGRAM_COMPLETE = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE,
MCB_WAT_DEBUG_ATTN = EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN,
MCB_DATA_ERROR = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR,

//XLT address valid offset
XLT0_SLOT1_D_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID,
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5 changes: 5 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H
View file
Expand Up @@ -300,6 +300,10 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST>

enum
{
// The start/end address config registers have common lengths and bits, just including 1 below
MCB_ADDR_CONFIG = MCBIST_MCBEA0Q_CFG_END_ADDR_0,
MCB_ADDR_CONFIG_LEN = MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN,

// Subtest control bits. These are the same in all '16 bit subtest' field
COMPL_1ST_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD,
COMPL_2ND_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD,
Expand Down Expand Up @@ -557,6 +561,7 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST>
MCB_WAT_DEBUG_ATTN = MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN,
MCB_PROGRAM_COMPLETE_MASK = MCB_PROGRAM_COMPLETE,
MCB_WAT_DEBUG_ATTN_MASK = MCB_WAT_DEBUG_ATTN,
MCB_DATA_ERROR = MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR,

//XLT address valid offset
XLT0_SLOT1_D_VALID = MCS_PORT13_MCP0XLT0_SLOT1_VALID,
Expand Down
105 changes: 104 additions & 1 deletion src/import/generic/memory/lib/utils/mcbist/gen_mss_mcbist.H
View file
Expand Up @@ -724,6 +724,41 @@ inline subtest_t<MC, T, TT> read_write_subtest()
return l_subtest;
}


///
/// @brief Return a write read subtest - configured simply
/// @tparam MC the mc type of the T
/// @tparam T the fapi2::TargetType - derived
/// @tparam TT the mcbistTraits associated with T - derived
/// @return mss::mcbist::subtest_t
/// @note Turns on ECC mode for the returned subtest - caller can turn it off
/// @note Configures for start/end address select bit as address config register 0
///
template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T = mss::mcbistMCTraits<MC>::MC_TARGET_TYPE, typename TT = mcbistTraits<MC, T> >
inline subtest_t<MC, T, TT> write_read_subtest()
{
// Starts life full of 0's
subtest_t<MC, T, TT> l_subtest;

// 0:3 = 0011 - we want subtest type to be a Write Read (WR)
l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::WRITE_READ);

// - Not a special subtest, so no other configs associated
// 4 = 0 - we don't want to complement data for our Writes
// 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix
// 7 = 0 - forward address generation
// 8 = 0 - non random address generation
// - Don't need to set up anything for LFSRs
// 9:11 = 000 - Fixed data mode

// 14:15 = 0 address select config registers 0

// By default we want to turn on ECC. Caller can turn it off.
l_subtest.change_ecc_mode(mss::ON);

return l_subtest;
}

///
/// @brief Return a read write read subtest - configured simply
/// @tparam MC the mc type of the T
Expand All @@ -739,7 +774,7 @@ inline subtest_t<MC, T, TT> read_write_read_subtest()
// Starts life full of 0's
subtest_t<MC, T, TT> l_subtest;

// 0:3 = 0100 - we want subtest type to be a Read Write Read (RWR) 7
// 0:3 = 0100 - we want subtest type to be a Read Write Read (RWR)
l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ_WRITE_READ);

// - Not a special subtest, so no other configs associated
Expand All @@ -758,6 +793,74 @@ inline subtest_t<MC, T, TT> read_write_read_subtest()
return l_subtest;
}

///
/// @brief Return a read read write subtest - configured simply
/// @tparam MC the mc type of the T
/// @tparam T the fapi2::TargetType - derived
/// @tparam TT the mcbistTraits associated with T - derived
/// @return mss::mcbist::subtest_t
/// @note Turns on ECC mode for the returned subtest - caller can turn it off
/// @note Configures for start/end address select bit as address config register 0
///
template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T = mss::mcbistMCTraits<MC>::MC_TARGET_TYPE, typename TT = mcbistTraits<MC, T> >
inline subtest_t<MC, T, TT> read_read_write_subtest()
{
// Starts life full of 0's
subtest_t<MC, T, TT> l_subtest;

// 0:3 = 1000 - we want subtest type to be a Read Read Write (RRW)
l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ_READ_WRITE);

// - Not a special subtest, so no other configs associated
// 4 = 0 - we don't want to complement data for our Writes
// 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix
// 7 = 0 - forward address generation
// 8 = 0 - non random address generation
// - Don't need to set up anything for LFSRs
// 9:11 = 000 - Fixed data mode

// 14:15 = 0 address select config registers 0

// By default we want to turn on ECC. Caller can turn it off.
l_subtest.change_ecc_mode(mss::ON);

return l_subtest;
}

///
/// @brief Return a read write write subtest - configured simply
/// @tparam MC the mc type of the T
/// @tparam T the fapi2::TargetType - derived
/// @tparam TT the mcbistTraits associated with T - derived
/// @return mss::mcbist::subtest_t
/// @note Turns on ECC mode for the returned subtest - caller can turn it off
/// @note Configures for start/end address select bit as address config register 0
///
template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T = mss::mcbistMCTraits<MC>::MC_TARGET_TYPE, typename TT = mcbistTraits<MC, T> >
inline subtest_t<MC, T, TT> read_write_write_subtest()
{
// Starts life full of 0's
subtest_t<MC, T, TT> l_subtest;

// 0:3 = 0101 - we want subtest type to be a Read Write Write (RWW)
l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ_WRITE_WRITE);

// - Not a special subtest, so no other configs associated
// 4 = 0 - we don't want to complement data for our Writes
// 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix
// 7 = 0 - forward address generation
// 8 = 0 - non random address generation
// - Don't need to set up anything for LFSRs
// 9:11 = 000 - Fixed data mode

// 14:15 = 0 address select config registers 0

// By default we want to turn on ECC. Caller can turn it off.
l_subtest.change_ecc_mode(mss::ON);

return l_subtest;
}

///
/// @brief Return a random subtest - configured simply
/// @tparam MC the mc type of the T
Expand Down

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