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PM: Enhance p9_pm_pss_init for reset error logging
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- Added informational error logs if failures were detected but the reset to the
  hardware proceeded anyway
- Done based on a P8 field observation where such logs would have been
  beneficial

Change-Id: I334887b178a0974def353fe2b98362fe87afd6ae
CQ: SW419455
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54941
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54943
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@stillgs @dcrowell77
stillgs authored and dcrowell77 committed Mar 16, 2018
1 parent 68f67bd commit 9b5cfe7
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Showing 3 changed files with 64 additions and 23 deletions.
44 changes: 24 additions & 20 deletions src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -36,6 +36,8 @@
// Includes
// -----------------------------------------------------------------------------
#include <p9_pm_pss_init.H>
#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fld.H>

// -----------------------------------------------------------------------------
// Function prototypes
Expand Down Expand Up @@ -310,14 +312,14 @@ fapi2::ReturnCode pm_pss_reset(
FAPI_TRY(fapi2::getScom(i_target, PU_SPIPSS_ADC_STATUS_REG, l_data64));

// ADC on-going complete
if (l_data64.getBit<0>() == 0)
if (l_data64.getBit<PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING>() == 0)
{
FAPI_INF("All frames sent from ADC to the APSS device.");
break;
}

// ADC error
FAPI_ASSERT(l_data64.getBit<7>() != 1,
FAPI_ASSERT(!l_data64.getBit<PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR>(),
fapi2::PM_PSS_ADC_ERROR()
.set_CHIP(i_target)
.set_POLLCOUNT(l_pollcount),
Expand All @@ -328,7 +330,7 @@ fapi2::ReturnCode pm_pss_reset(
}

// Write attempted while Bridge busy
if(l_data64.getBit<5>() == 1)
if(l_data64.getBit<PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR>() == 1)
{
FAPI_INF("SPIP2S Write While Bridge Busy bit asserted. May cause "
"undefined bridge behavior. Will be cleared during reset");
Expand Down Expand Up @@ -360,7 +362,7 @@ fapi2::ReturnCode pm_pss_reset(
}

// P2S error
FAPI_ASSERT(l_data64.getBit<7>() != 1,
FAPI_ASSERT(!l_data64.getBit<PU_SPIPSS_P2S_STATUS_REG_FSM_ERR>(),
fapi2::PM_PSS_P2S_ERROR()
.set_CHIP(i_target)
.set_POLLCOUNT(l_pollcount),
Expand All @@ -370,19 +372,20 @@ fapi2::ReturnCode pm_pss_reset(
fapi2::delay(l_pss_poll_interval_us * 1000, 1000);
}

// write attempted while bridge busy
if (l_data64.getBit<5>() == 1)
{
FAPI_INF("SPIP2S Write While Bridge Busy bit asserted. "
"Will be cleared with coming reset");
}

// Poll timeout
if (l_pollcount >= l_max_polls)
{
FAPI_INF("WARNING: SPI P2S did not go to idle in at least %d us. "
"Reset of PSS macro is commencing anyway", l_pss_timeout_us);
}
FAPI_ASSERT_NOEXIT(!l_data64.getBit<PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR>(),
fapi2::PM_PSS_ADC_WRITE_WHILE_BUSY()
.set_CHIP(i_target)
.set_POLLCOUNT(l_pollcount),
"SPIP2S Write While Bridge Busy bit asserted. Will be cleared with coming reset");

FAPI_ASSERT_NOEXIT(l_pollcount < l_max_polls,
fapi2::PM_PSS_ADC_TIMEOUT()
.set_CHIP(i_target)
.set_POLLCOUNT(l_pollcount)
.set_MAXPOLLS(l_max_polls)
.set_TIMEOUTUS(l_pss_timeout_us),
"SPI P2S did not go to idle in at least % d us. "
"Reset of PSS macro is commencing anyway", l_pss_timeout_us );

// ******************************************************************
// - Resetting both ADC and P2S bridge
Expand All @@ -391,7 +394,8 @@ fapi2::ReturnCode pm_pss_reset(
FAPI_INF("Resetting P2S and ADC bridges.");

l_data64.flush<0>();
l_data64.setBit<1>();
// Need to write 01
l_data64.setBit < PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL + 1 > ();

FAPI_TRY(fapi2::putScom(i_target, PU_SPIPSS_ADC_RESET_REGISTER, l_data64),
"Error: Could not reset ADC bridge");
Expand All @@ -406,6 +410,6 @@ fapi2::ReturnCode pm_pss_reset(
"Error: Could not clear the P2S reset register");

fapi_try_exit:
FAPI_IMP("<< pm_pss_reset");
FAPI_IMP(" << pm_pss_reset");
return fapi2::current_err;
}
3 changes: 1 addition & 2 deletions src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -78,7 +78,6 @@
//------------------------------------------------------------------------------
#include <fapi2.H>
#include <p9_pm.H>
#include <p9_misc_scom_addresses.H>

typedef fapi2::ReturnCode (*p9_pm_pss_init_FP_t)
(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
Expand Down
40 changes: 39 additions & 1 deletion src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand Down Expand Up @@ -54,6 +54,44 @@
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_ADC_WRITE_WHILE_BUSY</rc>
<description>SPI ADC was written while the bridge was busy. Cleared with
coming reset.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CODE</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_ADC_TIMEOUT</rc>
<description>SPIADC timed waiting to be quiesced. The SPIADC will be reset
anyway so as to attempt to recover the interface.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<ffdc>MAXPOLLS</ffdc>
<ffdc>TIMEOUTUS</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_P2S_ERROR</rc>
<description>SPIP2S error bit asserted waiting for operation to complete.
Expand Down

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