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Adds power control access functions for NVDIMM
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Change-Id: Id72258da03e1e54a6edf2995a50dd25b3ede9a14
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55061
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55153
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@sglancy6 @dcrowell77
sglancy6 authored and dcrowell77 committed Mar 9, 2018
1 parent 63c767d commit a61200c
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Showing 2 changed files with 199 additions and 6 deletions.
10 changes: 5 additions & 5 deletions src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -89,7 +89,7 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
fapi2::buffer<uint64_t> l_data;

FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl), "Error in set_pwr_cntrl_reg");
FAPI_TRY(mss::getScom(i_target, MCA_MBARPC0Q, l_data), "Error in set_pwr_cntrl_reg");
FAPI_TRY(read_mbarpc0(i_target, l_data));

l_data.insertFromRight<TT::CFG_MIN_MAX_DOMAINS, TT::CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MINALL);

Expand Down Expand Up @@ -117,7 +117,7 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
l_data.insertFromRight<TT::MIN_DOMAIN_REDUCTION_TIME, TT::MIN_DOMAIN_REDUCTION_TIME_LEN>
(MIN_DOMAIN_REDUCTION_TIME);

FAPI_TRY(mss::putScom(i_target, MCA_MBARPC0Q, l_data), "Error in set_pwr_cntrl_reg" );
FAPI_TRY(write_mbarpc0(i_target, l_data));

return fapi2::FAPI2_RC_SUCCESS;
fapi_try_exit:
Expand All @@ -138,7 +138,7 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar
fapi2::buffer<uint64_t> l_data;

FAPI_TRY(mrw_power_control_requested(l_str_enable), "Error in set_pwr_cntrl_reg");
FAPI_TRY(mss::getScom(i_target, MCA_MBASTR0Q, l_data), "Error in set_pwr_cntrl_reg");
FAPI_TRY(read_mbastr0(i_target, l_data));

//Write bit if STR should be enabled
switch (l_str_enable)
Expand All @@ -162,7 +162,7 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar

l_data.insertFromRight<TT::ENTER_STR_TIME_POS, TT::ENTER_STR_TIME_LEN>(ENTER_STR_TIME);

FAPI_TRY(mss::putScom(i_target, MCA_MBASTR0Q, l_data), "Error in set_str_reg" );
FAPI_TRY(write_mbastr0(i_target, l_data));

return fapi2::FAPI2_RC_SUCCESS;
fapi_try_exit:
Expand Down
195 changes: 194 additions & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -42,6 +42,7 @@
#include <p9_mc_scom_addresses_fld.H>
#include <lib/mss_attribute_accessors.H>
#include <lib/dimm/kind.H>
#include <lib/shared/mss_const.H>
#include <generic/memory/lib/utils/scom.H>

namespace mss
Expand Down Expand Up @@ -77,6 +78,10 @@ class mcTraits<fapi2::TARGET_TYPE_MCA>
public:
enum
{
// Register definitions
MBARPC0 = MCA_MBARPC0Q,
MBASTR0 = MCA_MBASTR0Q,

SLOT0_VALID = MCS_PORT02_MCP0XLT0_SLOT0_VALID,
SLOT0_ROW15_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID,
SLOT0_M1_VALID = MCS_PORT02_MCP0XLT0_SLOT0_M1_VALID,
Expand Down Expand Up @@ -183,6 +188,194 @@ enum
namespace mc
{

///
/// @brief Reads the contents of the MBARPC0
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_target the target on which to operate
/// @param[out] o_data the register data
/// @return fapi2::fapi2_rc_success if ok
///
template< fapi2::TargetType T, typename TT = mcTraits<T> >
inline fapi2::ReturnCode read_mbarpc0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
o_data = 0;

FAPI_TRY( mss::getScom(i_target, TT::MBARPC0, o_data ), "%s failed to read MBARPC0 regiser", mss::c_str(i_target));
FAPI_DBG("%s MBARPC0 has data 0x%016lx", mss::c_str(i_target), o_data);

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Writes the contents of the MBARPC0
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_target the target on which to operate
/// @param[in] i_data the register data
/// @return fapi2::fapi2_rc_success if ok
///
template< fapi2::TargetType T, typename TT = mcTraits<T> >
inline fapi2::ReturnCode write_mbarpc0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
{
FAPI_TRY( mss::putScom(i_target, TT::MBARPC0, i_data ), "%s failed to write MBARPC0 regiser", mss::c_str(i_target));
FAPI_DBG("%s MBARPC0 has data 0x%016lx", mss::c_str(i_target), i_data);

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Sets the power control enable bit
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in,out] io_data the value of the register
/// @param[in] i_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void set_power_control_min_max_domains_enable( fapi2::buffer<uint64_t>& io_data, const mss::states i_state )
{
FAPI_DBG("set_power_control_min_max_domains_enable to %d", i_state);
io_data.writeBit<TT::MIN_MAX_DOMAINS_ENABLE>(i_state == mss::states::ON);
}

///
/// @brief Gets the power control enable bit
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_data the value of the register
/// @param[out] o_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void get_power_control_min_max_domains_enable( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state )
{
o_state = i_data.getBit<TT::MIN_MAX_DOMAINS_ENABLE>() ? mss::states::ON : mss::states::OFF;
FAPI_DBG("get_power_control_min_max_domains_enable to %d", o_state, TT::MIN_DOMAIN_REDUCTION_ENABLE);
}

///
/// @brief Sets the power control min max domains
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in,out] io_data the value of the register
/// @param[in] i_value the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void set_power_control_min_max_domains( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value )
{
FAPI_DBG("set_power_control_min_max_domains to %d", i_value);
io_data.insertFromRight<TT::CFG_MIN_MAX_DOMAINS, TT::CFG_MIN_MAX_DOMAINS_LEN>(i_value);
}

///
/// @brief Gets the power control min max domains
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_data the value of the register
/// @param[out] o_value the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void get_power_control_min_max_domains( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value )
{
i_data.extractToRight<TT::CFG_MIN_MAX_DOMAINS, TT::CFG_MIN_MAX_DOMAINS_LEN>(o_value);
FAPI_DBG("get_power_control_min_max_domains to %d", o_value);
}

///
/// @brief Sets the power control minimum domain reduction enable
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in,out] io_data the value of the register
/// @param[in] i_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void set_power_control_min_domain_reduction_enable( fapi2::buffer<uint64_t>& io_data, const mss::states i_state )
{
io_data.writeBit<TT::MIN_DOMAIN_REDUCTION_ENABLE>(i_state == mss::states::ON);
FAPI_DBG("set_power_control_min_domain_reduction_enable to %d 0x%016lx", i_state, io_data);
}

///
/// @brief Gets the power control minimum domain reduction enable
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_data the value of the register
/// @param[out] o_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void get_power_control_min_domain_reduction_enable( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state )
{
o_state = i_data.getBit<TT::MIN_DOMAIN_REDUCTION_ENABLE>() ? mss::states::ON : mss::states::OFF;
FAPI_DBG("get_power_control_min_domain_reduction_enable to %d", o_state);
}

///
/// @brief Reads the contents of the MBASTR0
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_target the target on which to operate
/// @param[out] o_data the register data
/// @return fapi2::fapi2_rc_success if ok
///
template< fapi2::TargetType T, typename TT = mcTraits<T> >
inline fapi2::ReturnCode read_mbastr0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
{
o_data = 0;

FAPI_TRY( mss::getScom(i_target, TT::MBASTR0, o_data ), "%s failed to read MBASTR0 regiser", mss::c_str(i_target));
FAPI_DBG("%s MBASTR0 has data 0x%016lx", mss::c_str(i_target), o_data);

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Writes the contents of the MBASTR0
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_target the target on which to operate
/// @param[in] i_data the register data
/// @return fapi2::fapi2_rc_success if ok
///
template< fapi2::TargetType T, typename TT = mcTraits<T> >
inline fapi2::ReturnCode write_mbastr0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
{
FAPI_TRY( mss::putScom(i_target, TT::MBASTR0, i_data ), "%s failed to write MBASTR0 regiser", mss::c_str(i_target));
FAPI_DBG("%s MBASTR0 has data 0x%016lx", mss::c_str(i_target), i_data);

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Sets the self time refresh enable bit
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in,out] io_data the value of the register
/// @param[in] i_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void set_self_time_refresh_enable( fapi2::buffer<uint64_t>& io_data, const mss::states i_state )
{
FAPI_DBG("set_power_control_min_domain_reduction_enable to %d", i_state);
io_data.writeBit<TT::CFG_STR_ENABLE>(i_state == mss::states::ON);
}

///
/// @brief Sets the self time refresh enable bit
/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
/// @tparam TT traits type defaults to mcTraits<T>
/// @param[in] i_data the value of the register
/// @param[out] o_state the state to write into the enable
///
template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
inline void get_self_time_refresh_enable( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state )
{
o_state = i_data.getBit<TT::CFG_STR_ENABLE>() ? mss::states::ON : mss::states::OFF;
FAPI_DBG("get_power_control_min_domain_reduction_enable to %d", o_state);
}

///
/// @brief set the PWR CNTRL register
/// @param[in] i_target the mca target
Expand Down

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