Remove logic to disable memory clocks in STR if in PD_AND_STR_CLK_STO…

…P mode

Do not disable memory clocks when in STR if power control mode
PD_AND_STR_CLK_STOP (ie.  treat it the same as PD_AND_STR).
Removing EC Chip level check since there isn't a current plan
for a RIT fix.

Change-Id: Ic3b3aff8868068e3997ae8af8fba53b6d7e3bd05
Original-Change-Id: I298561c39a2419ed7f92e90c9eeaf8924fc412bc
CQ:HW416315
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45653
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55568
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -4309,24 +4309,6 @@
     </chipEcFeature>
   </attribute>
 
-  <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_DIS_CLK_IN_STR</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Only set the disable memory clock stop when in STR for DD2.*
-      Doesn't work for DD1.*
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>LESS_THAN</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_PERIODICS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>