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Add SPD, ATTR, and code support for thermal sensor fields
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In order to not break systems with old DDIMMs or old Explorer FW,
this commit includes a workaround to bypass the thermal field parsing
if the SPD revision is less than 0.3, as the decoder will try to
parse garbage. This can be replaced down the line if needed with
a proper API.

git-coreq:hostboot:I7400886b90b566bbfdf218bcedf11627acf1d2fd
Change-Id: I7400886b90b566bbfdf218bcedf11627acf1d2fd
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87999
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88584
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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@markypizz @dcrowell77
markypizz authored and dcrowell77 committed Feb 25, 2020
1 parent 4a69880 commit ac2efc8
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Showing 19 changed files with 2,522 additions and 79 deletions.
102 changes: 102 additions & 0 deletions src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_attr_engine_traits.H
View file
Expand Up @@ -1219,6 +1219,57 @@ struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_f
}
};

//
/// @brief Traits for attr_engine
/// @class attrEngineTraits
/// @tparam P processor type
/// @note P, pmic::attr_eff_engine_fields, PMIC0_REDUNDANCY partial specialization
///
template< proc_type P>
struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_REDUNDANCY>
{
using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_REDUNDANCY_Type;
using attr_integral_type = std::remove_all_extents<attr_type>::type;
static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_REDUNDANCY_TargetType;
static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_REDUNDANCY;

///
/// @brief attribute getter
/// @param[in] i_target the fapi2 target
/// @param[out] o_setting array to populate
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
attr_type& o_setting)
{
return attr::get_pmic0_redundancy(i_target, o_setting);
}

///
/// @brief attribute setter
/// @param[in] i_target the fapi2 target
/// @param[in] i_setting array to set
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
attr_type& i_setting)
{
return attr::set_pmic0_redundancy(i_target, i_setting);
}

///
/// @brief Computes setting for attribute
/// @param[in] i_spd_data EFD data
/// @param[out] o_setting value we want to set attr with
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
attr_integral_type& o_setting)
{
return i_spd_data.pmic0_redundancy(o_setting);
}
};


//----------------------------------------
// PMIC 1
Expand Down Expand Up @@ -2378,6 +2429,57 @@ struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_f
}
};

//
/// @brief Traits for attr_engine
/// @class attrEngineTraits
/// @tparam P processor type
/// @note P, pmic::attr_eff_engine_fields, PMIC1_REDUNDANCY partial specialization
///
template< proc_type P>
struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_REDUNDANCY>
{
using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_REDUNDANCY_Type;
using attr_integral_type = std::remove_all_extents<attr_type>::type;
static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_REDUNDANCY_TargetType;
static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_REDUNDANCY;

///
/// @brief attribute getter
/// @param[in] i_target the fapi2 target
/// @param[out] o_setting array to populate
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target,
attr_type& o_setting)
{
return attr::get_pmic1_redundancy(i_target, o_setting);
}

///
/// @brief attribute setter
/// @param[in] i_target the fapi2 target
/// @param[in] i_setting array to set
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target,
attr_type& i_setting)
{
return attr::set_pmic1_redundancy(i_target, i_setting);
}

///
/// @brief Computes setting for attribute
/// @param[in] i_spd_data EFD data
/// @param[out] o_setting value we want to set attr with
/// @return FAPI2_RC_SUCCESS iff okay
///
static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data,
attr_integral_type& o_setting)
{
return i_spd_data.pmic1_redundancy(o_setting);
}
};

//
/// @brief Traits for attr_engine
/// @class attrEngineTraits
Expand Down
8 changes: 7 additions & 1 deletion src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H
View file
Expand Up @@ -163,8 +163,11 @@ enum class attr_eff_engine_fields
PMIC0_SEQUENCE = 45,
PMIC1_SEQUENCE = 46,

PMIC0_REDUNDANCY = 47,
PMIC1_REDUNDANCY = 48,

// Dispatcher set to last enum value
DISPATCHER = PMIC1_SEQUENCE,
DISPATCHER = PMIC1_REDUNDANCY,
};

///
Expand Down Expand Up @@ -228,6 +231,9 @@ enum ffdc_codes

SET_PMIC0_SEQUENCE = 0x107E,
SET_PMIC1_SEQUENCE = 0x107F,

SET_PMIC0_REDUNDANCY = 0x1080,
SET_PMIC1_REDUNDANCY = 0x1081,
};

///
Expand Down
32 changes: 32 additions & 0 deletions src/import/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml
View file
Expand Up @@ -528,6 +528,22 @@
<mssAccessorName>pmic1_swd_sequence_order</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MEM_EFF_PMIC0_REDUNDANCY</id>
<targetType>TARGET_TYPE_OCMB_CHIP</targetType>
<description>
Redundant PMIC exists for PMIC0
</description>
<enum>
DISABLED = 0,
ENABLED = 1
</enum>
<valueType>uint8</valueType>
<writeable/>
<initToZero></initToZero>
<mssAccessorName>pmic0_redundancy</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MEM_EFF_PMIC0_PHASE_COMB</id>
<targetType>TARGET_TYPE_OCMB_CHIP</targetType>
Expand All @@ -540,6 +556,22 @@
<mssAccessorName>pmic0_phase_comb</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MEM_EFF_PMIC1_REDUNDANCY</id>
<targetType>TARGET_TYPE_OCMB_CHIP</targetType>
<description>
Redundant PMIC exists for PMIC1
</description>
<enum>
DISABLED = 0,
ENABLED = 1
</enum>
<valueType>uint8</valueType>
<writeable/>
<initToZero></initToZero>
<mssAccessorName>pmic1_redundancy</mssAccessorName>
</attribute>

<attribute>
<id>ATTR_MEM_EFF_PMIC1_PHASE_COMB</id>
<targetType>TARGET_TYPE_OCMB_CHIP</targetType>
Expand Down
17 changes: 13 additions & 4 deletions src/import/chips/ocmb/common/spd_access/pmic_i2c_addr_get.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -47,22 +47,31 @@

constexpr uint16_t SPD_PMIC0_I2C_BYTE = 260;
constexpr uint16_t SPD_PMIC1_I2C_BYTE = 261;
constexpr uint16_t SPD_PMIC0_REDUNDANT_I2C_BYTE = 262;
constexpr uint16_t SPD_PMIC1_REDUNDANT_I2C_BYTE = 263;

// Since we'll pass in numbers 0-3 we'll denote the PMICs as such,
// PMIC2 = redundant 0
// PMIC3 = redundant 1
constexpr uint8_t PMIC0 = 0;
constexpr uint8_t PMIC1 = 1;
constexpr uint8_t PMIC2 = 2;
constexpr uint8_t PMIC3 = 3;

// Mapping from PMIC ID to SPD byte
static const std::vector<uint16_t> PMIC_I2C_ADDR_VECTOR =
{
SPD_PMIC0_I2C_BYTE, // [0 == PMIC0]
SPD_PMIC1_I2C_BYTE // [1 == PMIC1]
SPD_PMIC0_I2C_BYTE, // 0 == PMIC0
SPD_PMIC1_I2C_BYTE, // 1 == PMIC1
SPD_PMIC0_REDUNDANT_I2C_BYTE, // 2 == PMIC2 (redundant 0)
SPD_PMIC1_REDUNDANT_I2C_BYTE, // 3 == PMIC3 (redundant 1)
};

///
/// @brief Get the pmic i2c address for the given PMIC ID
///
/// @param[in] i_spd SPD binary
/// @param[in] i_pmic_id PMIC ID (0,1)
/// @param[in] i_pmic_id PMIC ID (0,1,2,3)
/// @return uint8_t I2C address for the given PMIC ID
/// @note May need to be changed to support 4U SPD
///
Expand Down
41 changes: 15 additions & 26 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.C
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -36,41 +36,30 @@
#include <fapi2.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/exp_mss_thermal_init_utils.H>
#include <lib/inband/exp_inband.H>
#include <exp_mss_thermal_init.H>
#include <generic/memory/lib/utils/find.H>

extern "C"
{

///
/// @brief Initializes thermal sensor
/// @param[in] i_target the controller target
/// @return FAPI2_RC_SUCCESS iff ok
///
///
/// @brief Initializes thermal sensor
/// @param[in] i_target the controller target
/// @return FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode exp_mss_thermal_init( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target )
{
FAPI_INF("%s Start thermal_init", mss::c_str(i_target));

#if 0
// Skip EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ until it's available in Explorer FW
// Declare variables
host_fw_command_struct l_cmd_sensor;
host_fw_response_struct l_response;
std::vector<uint8_t> l_rsp_data;

// Sets up EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ cmd params
mss::exp::setup_sensor_interval_read_cmd_params(l_cmd_sensor);
uint8_t l_interval_read_dis = 0;
FAPI_TRY(mss::attr::get_disable_therm_init_read(i_target, l_interval_read_dis));

// Enable sensors
FAPI_TRY( mss::exp::ib::putCMD(i_target, l_cmd_sensor),
"Failed putCMD() for %s", mss::c_str(i_target) );

FAPI_TRY( mss::exp::ib::getRSP(i_target, l_response, l_rsp_data),
"Failed getRSP() for %s", mss::c_str(i_target) );

FAPI_TRY( mss::exp::check::sensor_response(i_target, l_response),
"Failed sensor_response() for %s", mss::c_str(i_target) );
#endif
// Attribute is 0 == enabled, 1 == disabled (enabled by default (0), make sure the disable is not set)
if (l_interval_read_dis == fapi2::ENUM_ATTR_MSS_OCMB_DISABLE_THERM_INIT_READ_ENABLED)
{
FAPI_TRY(mss::exp::sensor_interval_read(i_target),
"Error performing EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ operation on %s", mss::c_str(i_target));
}

#ifdef __HOSTBOOT_MODULE
// Prior to starting OCC, we go into "safemode" throttling
Expand Down

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