enable prefetch drop for better MC fairness

Change-Id: I0fee2fe19b703e090ad2364a2a38dac31079b38f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37010 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37101 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
open-power · Mar 2, 2017 · ad4305c · ad4305c
1 parent 420ca4a
commit ad4305c
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Showing 3 changed files with 40 additions and 5 deletions.
diff --git a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
@@ -76,26 +76,40 @@ target_type 2 TARGET_TYPE_PROC_CHIP;
 ##########################
 
 # If cache scope prediciton logic is active, must disable fp_m bit, so fp ops will go fetch 128 bytes (for potential mdi update)
-espy  MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_FP_M_BIT [when=S] {
+espy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_FP_M_BIT [when=S] {
   spyv;
   ON;
 }
 
 # HW376110
-ispy  MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW376110] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW376110] {
   spyv;
   0b0111;
 }
 
 # Turns off SRQ pf drop
-ispy  MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_SRQ [when=S] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_SRQ [when=S] {
   spyv;
   0;
 }
 
 # HW400075 Always set MDI to 1 for ttypes cp_me and cp_m
-ispy  MC01.PBI01.SCOMFIR.MCMODE2_DISABLE_MDI0 [when=S && ATTR_CHIP_EC_FEATURE_HW40075] {
+ispy MC01.PBI01.SCOMFIR.MCMODE2_DISABLE_MDI0 [when=S && ATTR_CHIP_EC_FEATURE_HW400075] {
   spyv,              expr;
   0b0001100000000,   (TGT1.ATTR_RISK_LEVEL == 0);
 }
 
+# HW398139 Enable commandlist prefetch drop for better arbitration
+# Prefetch drop references an internal counter (6 by default - this is max value) to determine
+# when a prefetch gets dropped. DROP_CNT_THRESH determines the rate the counter decrements (in units
+# of 4 nest clocks) -- here, 8 * 4 nclks = 32 nclks, 32 nclks * 6 counts => takes 192 nest clocks
+# to drop a prefetch. This dial may need to be tuned for performance.
+espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_CMDLIST [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+  spyv;
+  ON;
+}
+
+ispy MC01.PBI01.SCOMFIR.MCPERF1_PF_DROP_CNT_THRESH [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+  spyv;
+  8;
+}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C
@@ -31,6 +31,7 @@ using namespace fapi2;
 
 constexpr uint64_t literal_0b0111 = 0b0111;
 constexpr uint64_t literal_0 = 0;
+constexpr uint64_t literal_8 = 8;
 constexpr uint64_t literal_0b0001100000000 = 0b0001100000000;
 
 fapi2::ReturnCode p9_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0,
@@ -49,6 +50,9 @@ fapi2::ReturnCode p9_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0,
 
             l_scom_buffer.insert<46, 4, 60, uint64_t>(literal_0b0111 );
             l_scom_buffer.insert<62, 1, 63, uint64_t>(literal_0 );
+            constexpr auto l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON = 0x1;
+            l_scom_buffer.insert<61, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON );
+            l_scom_buffer.insert<32, 7, 57, uint64_t>(literal_8 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010810ull, l_scom_buffer));
         }
         {

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2319,7 +2319,7 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW40075</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW400075</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues.
@@ -2335,6 +2335,23 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW398139</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>