STOP API: Changes for SMF and SPR self save

    Commit accomplishes following:
        -   Implementation of new self restore region memory layout
        -   Restore of SPRs pertaining to SMF
        -   Self save of SPRs
        -   Backward compatibility with old self restore layout
Key_Cronus_Test=PM_REGRESS

Change-Id: I11359e392102d32896251225907eb95a43ba6f78
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66212
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66216
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H

@@ -311,6 +311,9 @@ HCD_CONST(CPMR_ATTN_WORD1_BYTE,                 0x04)
 HCD_CONST(CPMR_MAGIC_NUMBER_BYTE,               0x08)
 HCD_CONST(CPMR_BUILD_DATE_BYTE,                 0x10)
 HCD_CONST(CPMR_BUILD_VER_BYTE,                  0x14)
+HCD_CONST(CPMR_SELF_RESTORE_VER_BYTE,           0x1C)
+HCD_CONST(CPMR_STOP_API_VER_BYTE,               0x1D)
+HCD_CONST(CPMR_URMOR_FIX_BYTE,                  0x1E)
 HCD_CONST(CPMR_CME_HCODE_OFFSET_BYTE,           0x20)
 HCD_CONST(CPMR_CME_HCODE_LENGTH_BYTE,           0x24)
 HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE,    0x28)
@@ -325,7 +328,7 @@ HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE,        0x48)
 HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE,        0x4C)
 HCD_CONST(CPMR_MAX_SCOM_REST_PER_CORE_BYTE,     0x50)
 
-/// Self Restore
+/// Self Restore without SMF Support
 
 HCD_CONST(SELF_RESTORE_CPMR_OFFSET,             CPMR_HEADER_SIZE)
 HCD_CONST(SELF_RESTORE_INT_SIZE,                (8 * ONE_KB))
@@ -344,7 +347,25 @@ HCD_CONST(SELF_RESTORE_CORE_REGS_SIZE,
 HCD_CONST(SELF_RESTORE_SIZE_TOTAL,
           (SELF_RESTORE_CODE_SIZE + SELF_RESTORE_CORE_REGS_SIZE))
 
-
+// Self Restore Region With SMF Support
+HCD_CONST(SMF_THREAD_LAUNCHER_SIZE,         1024)
+HCD_CONST(SMF_SELF_RESTORE_CODE_SIZE,
+          (SELF_RESTORE_INT_SIZE + SMF_THREAD_LAUNCHER_SIZE))
+
+HCD_CONST(SMF_CORE_RESTORE_THREAD_AREA_SIZE,         HALF_KB)
+HCD_CONST(SMF_SELF_SAVE_THREAD_AREA_SIZE,            256)
+HCD_CONST(SMF_CORE_RESTORE_CORE_AREA_SIZE,           HALF_KB)
+HCD_CONST(SMF_CORE_SAVE_CORE_AREA_SIZE,              HALF_KB)
+
+HCD_CONST(SMF_SELF_RESTORE_CORE_REGS_SIZE,
+          MAX_CORES_PER_CHIP * ((SMF_CORE_RESTORE_THREAD_AREA_SIZE* MAX_THREADS_PER_CORE ) +
+                                (SMF_SELF_SAVE_THREAD_AREA_SIZE*     MAX_THREADS_PER_CORE ) +
+                                SMF_CORE_RESTORE_CORE_AREA_SIZE +
+                                SMF_CORE_SAVE_CORE_AREA_SIZE ))
+
+HCD_CONST(SMF_SELF_RESTORE_SIZE_TOTAL,
+          (SMF_SELF_RESTORE_CODE_SIZE + SMF_SELF_RESTORE_CORE_REGS_SIZE))
+HCD_CONST( EC_LEVEL_URMOR_FIX, 0x23 )
 /// Core Scom
 
 HCD_CONST(CORE_SCOM_RESTORE_CPMR_OFFSET,        (256 * ONE_KB))

src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H

@@ -50,21 +50,32 @@ namespace stopImageSection
  */
 enum
 {
-    ORI_OPCODE        = 24,
-    RFI_OPCODE        = 19,
-    RFI_CONST         = 50,
-    ORIS_OPCODE       = 25,
-    OPCODE_31         = 31,
-    XOR_CONST         = 316,
-    RLDICR_OPCODE     = 30,
-    RLDICR_CONST      = 1,
-    MTSPR_CONST1      = 467,
-    MTMSRD_CONST1     = 178,
-    MR_R0_TO_R10      = 0x7c0a0378, //mr r10, r0
-    MR_R0_TO_R21      = 0x7c150378, //mr r21, r0
-    BLR_INST          = 0x4e800020,
-    MTSPR_BASE_OPCODE = 0x7c0003a6,
-    ATTN_OPCODE       = 0x00000200,
+    ORI_OPCODE          =   24,
+    RFI_OPCODE          =   19,
+    RFI_CONST           =   50,
+    MFMSR_CONST         =   83,
+    ORIS_OPCODE         =   25,
+    OPCODE_31           =   31,
+    XOR_CONST           =   316,
+    RLDICR_OPCODE       =   30,
+    RLDICR_CONST        =   1,
+    MTSPR_CONST1        =   467,
+    MTMSRD_CONST1       =   178,
+    MR_R0_TO_R10        =   0x7c0a0378, //mr r10, r0
+    MR_R0_TO_R21        =   0x7c150378, //mr r21, r0
+    MR_R0_TO_R9         =   0x7c090378, //mr r9, r0
+    URMOR_CORRECTION    =   0x7d397ba6,
+    MFSPR_CONST         =   339,
+    BLR_INST            =   0x4e800020,
+    MTSPR_BASE_OPCODE   =   0x7c0003a6,
+    ATTN_OPCODE         =   0x00000200,
+    OPCODE_18           =   18,
+    SELF_SAVE_FUNC_ADD  =   0x2300,
+    SELF_SAVE_OFFSET    =   0x180,
+    SKIP_SPR_REST_INST  =   0x4800001c, //b . +0x01c
+    MFLR_R30            =   0x7fc802a6,
+    SKIP_SPR_SELF_SAVE  =   0x3bff0020, //addi r31 r31, 0x20
+    MTLR_INST           =   0x7fc803a6  //mtlr r30
 };
 
 #ifdef __cplusplus