Turn off PHY refresh for RD_CNTR - RD_VREF

Change-Id: Id7ca905dc984fdf1cd8070ffd55ed08031522f45
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41049
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41058
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C

@@ -50,6 +50,7 @@
 #include <lib/workarounds/wr_vref_workarounds.H>
 #include <lib/dimm/ddr4/latch_wr_vref.H>
 #include <lib/workarounds/seq_workarounds.H>
+#include <lib/workarounds/dqs_align_workarounds.H>
 
 #include <lib/utils/bit_count.H>
 #include <generic/memory/lib/utils/find.H>
@@ -1074,7 +1075,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         l_steps_to_execute.setBit<mss::cal_steps::DQS_ALIGN>();
         l_steps_to_execute.writeBit<mss::cal_steps::INITIAL_PAT_WR>(i_cal_steps_enabled.getBit<mss::cal_steps::WR_LEVEL>());
 
-        FAPI_INF("%s Running DQS align on RP%d 0x%04x",
+        FAPI_INF("%s Running DQS align on RP%d 0x%08lx",
                  mss::c_str(i_target), i_rp, l_steps_to_execute);
 
         // Undertake the calibration steps
@@ -1083,19 +1084,24 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         // Now run the DQS align workaround
         FAPI_TRY(mss::workarounds::dp16::dqs_align::dqs_align_workaround(i_target, i_rp, i_abort_on_error),
                  "%s Failed to run dqs align workaround on rp %d", mss::c_str(i_target), i_rp);
+
+
     }
 
     // Run cal steps between RDCLK_ALIGN and RD_CTR if any are selected - note RDCLK_ALIGN takes place after WR_LEVEL
     if (i_cal_steps_enabled.getBit<mss::cal_steps::RDCLK_ALIGN, mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN>())
     {
+        // Turn off refresh
+        FAPI_TRY( mss::workarounds::dqs_align::turn_off_refresh(i_target) );
+
         // Sets up the cal steps in the buffer
         fapi2::buffer<uint32_t> l_steps_to_execute;
 
         i_cal_steps_enabled.extract<mss::cal_steps::RDCLK_ALIGN,
                                     mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN,
                                     mss::cal_steps::RDCLK_ALIGN>(l_steps_to_execute);
 
-        FAPI_INF("%s Running rd_clk align through read centering vref on RP%d 0x%04x", mss::c_str(i_target), i_rp,
+        FAPI_INF("%s Running rd_clk align through read centering vref on RP%d 0x%08lx", mss::c_str(i_target), i_rp,
                  l_steps_to_execute);
 
         // Undertake the calibration steps
@@ -1107,19 +1113,22 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
             FAPI_TRY(mss::workarounds::dp16::rd_dq::fix_delay_values(i_target, i_rp),
                      "%s Failed to run read centering workaround on rp %d", mss::c_str(i_target), i_rp);
         }
+
+        // Turn refresh back on
+        FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(i_target) );
     }
 
     // Run cal steps after RD_CTR if any are selected - note: WRITE_CTR takes place after RD_CTR
     if (i_cal_steps_enabled.getBit<mss::cal_steps::WRITE_CTR, mss::cal_steps::WR_VREF_TO_COARSE_RD_LEN>())
     {
-        FAPI_DBG("%s Running remaining cal steps on RP%d", mss::c_str(i_target), i_rp);
-        fapi2::buffer<uint32_t> l_steps_to_execute = i_cal_steps_enabled;
-
-        // Clear all steps we've run previously
-        l_steps_to_execute.clearBit<mss::cal_steps::DRAM_ZQCAL>()
-        .clearBit<mss::cal_steps::WR_LEVEL>()
-        .clearBit<mss::cal_steps::INITIAL_PAT_WR>()
-        .clearBit<mss::cal_steps::RDCLK_ALIGN, mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN>();
+        fapi2::buffer<uint32_t> l_steps_to_execute( i_cal_steps_enabled );
+        l_steps_to_execute.clearBit<mss::cal_steps::DRAM_ZQCAL, mss::cal_steps::DRAM_ZQCAL_TO_WRITE_CTR_2D_VREF>();
+
+        // Setting the WR_VREF_LATCH bit to run the WR_VREF workaround after wr_vref runs
+        // Gets set iff the bit is set in i_steps_to_execute
+        l_steps_to_execute.writeBit<WR_VREF_LATCH>( i_cal_steps_enabled.getBit<WR_VREF_LATCH>() );
+
+        FAPI_DBG("%s Running remaining cal steps on RP%d 0x%08lx", mss::c_str(i_target), i_rp, l_steps_to_execute);
 
         FAPI_TRY( execute_cal_steps_helper(i_target, i_rp, l_steps_to_execute, i_abort_on_error) );
     }

src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H

@@ -177,6 +177,7 @@ enum cal_steps : uint64_t
     INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR),
     WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD),
     RDCLK_ALIGN_TO_RD_CTR_LEN = inclusive_range(RDCLK_ALIGN, READ_CTR),
+    DRAM_ZQCAL_TO_WRITE_CTR_2D_VREF = inclusive_range(DRAM_ZQCAL, WRITE_CTR_2D_VREF),
 };
 
 // Static consts for DDR4 voltages used in p9_mss_volt

src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.C

@@ -25,6 +25,8 @@
 
 #include <fapi2.H>
 #include <lib/workarounds/dqs_align_workarounds.H>
+#include <p9_mc_scom_addresses.H>
+#include <mss_attribute_accessors.H>
 #include <lib/phy/seq.H>
 #include <lib/phy/phy_cntrl.H>
 
@@ -85,12 +87,33 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Clear the PHY sequencer refresh
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+fapi2::ReturnCode clear_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
+{
+    // Turns off refresh
+    constexpr size_t REF_CNTL = 0b00;
+
+    fapi2::buffer<uint64_t> l_data;
+    FAPI_TRY( mss::pc::read_init_cal_config1(i_target, l_data) );
+
+    mss::pc::set_refresh_control(l_data, REF_CNTL);
+
+    FAPI_TRY( mss::pc::write_init_cal_config1(i_target, l_data) )
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 ///
 /// @brief Set PHY sequencer to trigger refresh during init cal
 /// @param[in] i_target the fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
-fapi2::ReturnCode refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
+fapi2::ReturnCode turn_on_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
 {
     uint8_t l_attr = 0;
     FAPI_TRY( mss::phy_seq_refresh(i_target, l_attr) );
@@ -111,6 +134,29 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Turn off refresh after dqs training has been run
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+fapi2::ReturnCode turn_off_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
+{
+    uint8_t l_attr = 0;
+    FAPI_TRY( mss::phy_seq_refresh(i_target, l_attr) );
+
+    if( l_attr == fapi2::ENUM_ATTR_MSS_PHY_SEQ_REFRESH_DISABLE )
+    {
+        FAPI_INF("Refresh for PHY sequencer is already off %s", mss::c_str(i_target));
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
+    FAPI_TRY( clear_init_cal_refresh(i_target),
+              "set_init_cal_refresh() failed for %s", mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 }
 }
 }

src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.H

@@ -27,8 +27,6 @@
 #define _MSS_WORKAROUNDS_DQS_ALIGN
 
 #include <fapi2.H>
-#include <p9_mc_scom_addresses.H>
-#include <mss_attribute_accessors.H>
 
 namespace mss
 {
@@ -53,12 +51,26 @@ fapi2::ReturnCode set_timing0_trfc(const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
 ///
 fapi2::ReturnCode set_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
 
+///
+/// @brief Clear the PHY sequencer refresh
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+fapi2::ReturnCode clear_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
+
 ///
 /// @brief Set PHY sequencer to trigger refresh during init cal
 /// @param[in] i_target the fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
-fapi2::ReturnCode refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
+fapi2::ReturnCode turn_on_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
+
+///
+/// @brief Turn off refresh after dqs training has been run
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+fapi2::ReturnCode turn_off_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
 
 }// dqs_align
 }// workarounds

src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C

@@ -170,12 +170,6 @@ extern "C"
         // Load MRS
         FAPI_TRY( mss::mrs_load(i_target) );
 
-        // DQS_ALIGN fail mitigation from Ryan King
-        for (const auto& p : l_mca)
-        {
-            FAPI_TRY( mss::workarounds::dqs_align::refresh(p) );
-        }
-
     fapi_try_exit:
         FAPI_INF("End draminit: %s (0x%lx)", mss::c_str(i_target), uint64_t(fapi2::current_err));
         return fapi2::current_err;

src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C

@@ -40,6 +40,7 @@
 #include <lib/utils/count_dimm.H>
 #include <lib/shared/mss_const.H>
 #include <lib/workarounds/dp16_workarounds.H>
+#include <lib/workarounds/dqs_align_workarounds.H>
 #include <lib/fir/unmask.H>
 #include <lib/dimm/ddr4/zqcal.H>
 
@@ -148,6 +149,9 @@ extern "C"
 
             FAPI_DBG("generating calibration CCS instructions: %d rank-pairs", l_pairs.size());
 
+            // Turn on refresh for training
+            FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(p) );
+
             // For each rank pair we need to calibrate, pop a ccs instruction in an array and execute it.
             // NOTE: IF YOU CALIBRATE MORE THAN ONE RANK PAIR PER CCS PROGRAM, MAKE SURE TO CHANGE
             // THE PROCESSING OF THE ERRORS. (it's hard to figure out which DIMM failed, too) BRS.