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NVDIMM RCD restore fix and zqcal timing fix
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-The original recipe uses the rcd_load() from draminit to restore the RCD.
But that would not work because the powerdown mode is enabled on the RCD
which causes it to ignore the commands. Also, special consideration is
required since this is being done with data in the DRAMs.

-Reduces zqcal delay for NVDIMM

Change-Id: Ic504f185ef770857bb1efbc9e3e4f61656a4ecdc
CQ:SW458516
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73507
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73519
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Tsung Yeung authored and dcrowell77 committed Mar 25, 2019
1 parent da2c809 commit c2a9006
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Showing 4 changed files with 320 additions and 19 deletions.
27 changes: 22 additions & 5 deletions src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -686,7 +686,8 @@ inline instruction_t<T> initial_cal_command(const uint64_t i_rp)
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline instruction_t<T> zqcl_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const uint64_t i_rank )
const uint64_t i_rank,
const uint16_t i_idle = 0 )
{
fapi2::buffer<uint64_t> l_boilerplate_arr0;
fapi2::buffer<uint64_t> l_boilerplate_arr1;
Expand All @@ -705,6 +706,9 @@ inline instruction_t<T> zqcl_command( const fapi2::Target<fapi2::TARGET_TYPE_DIM
// ADDR10/AP is high
l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_10>();

// Insert idle
l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle );

return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1);
}

Expand Down Expand Up @@ -870,14 +874,16 @@ inline instruction_t<T> rda_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] i_target the DIMM this instruction is headed for
/// @param[in] i_rank the rank on this dimm
/// @param[in] i_idle the idle time to the next command (default to 0)
/// @return the precharge all banks command CCS instruction
/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this
/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included
/// in this template definition)
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const uint64_t i_rank )
const uint64_t i_rank,
const uint16_t i_idle = 0 )
{
fapi2::buffer<uint64_t> l_boilerplate_arr0;
fapi2::buffer<uint64_t> l_boilerplate_arr1;
Expand All @@ -896,6 +902,9 @@ inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET
// Setup ADDR10/AP high
l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_10>();

// Insert idle
l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle );

// From DDR4 Spec table 17:
// All other bits from the command truth table or 'V', for valid (1 or 0)

Expand All @@ -908,12 +917,13 @@ inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] i_target the DIMM this instruction is headed for
/// @param[in] i_rank the rank on this dimm
/// @param[in] i_idle the idle time to the next command (default to 0)
/// @return the self-refresh entry command CCS instruction
/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline instruction_t<T> self_refresh_entry_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const uint64_t i_rank )
const uint64_t i_rank, const uint16_t i_idle = 0 )
{
fapi2::buffer<uint64_t> l_boilerplate_arr0;
fapi2::buffer<uint64_t> l_boilerplate_arr1;
Expand All @@ -929,6 +939,9 @@ inline instruction_t<T> self_refresh_entry_command( const fapi2::Target<fapi2::T
.template clearBit<TT::ARR0_DDR_ADDRESS_15>()
.template setBit<TT::ARR0_DDR_ADDRESS_14>();

// Insert idle
l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle );

// From DDR4 Spec table 17:
// All other bits from the command truth table are 'V', for valid (1 or 0)

Expand All @@ -941,13 +954,14 @@ inline instruction_t<T> self_refresh_entry_command( const fapi2::Target<fapi2::T
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] i_target the DIMM this instruction is headed for
/// @param[in] i_rank the rank on this dimm
/// @param[in] i_idle the idle time to the next command (default to 0)
/// @return the self-refresh exit command CCS instruction
/// @note Using NOP in case SDRAM is in gear down mode and max power saving mode exit
/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline instruction_t<T> self_refresh_exit_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const uint64_t i_rank )
const uint64_t i_rank, const uint16_t i_idle = 0 )
{
fapi2::buffer<uint64_t> l_boilerplate_arr0;
fapi2::buffer<uint64_t> l_boilerplate_arr1;
Expand All @@ -963,6 +977,9 @@ inline instruction_t<T> self_refresh_exit_command( const fapi2::Target<fapi2::TA
.template setBit<TT::ARR0_DDR_ADDRESS_15>()
.template setBit<TT::ARR0_DDR_ADDRESS_14>();

// Insert idle
l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle );

// From DDR4 Spec table 17:
// All other bits from the command truth table are 'V', for valid (1 or 0)

Expand Down

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