Add Explorer specific MCBIST settings before scrub and maint

Change-Id: Ieabf8b23b6670ed23664ce2f80b04012c05a4319
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90287
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90317
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C

@@ -93,7 +93,7 @@ extern "C"
         FAPI_TRY( mss::enable_zq_cal(i_target), "%s Failed enable_zq_cal", mss::c_str(i_target) );
 
         // Enable ecc checking
-        FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );
+        FAPI_TRY( mss::enable_read_ecc<mss::mc_type::EXPLORER>(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );
 
         // Apply marks from OCMB VPD
         FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) );

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C

@@ -22,3 +22,60 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_port.C
+/// @brief Code to support ports
+///
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: HB:FSP
+
+#include <fapi2.H>
+#include <lib/shared/exp_defaults.H>
+#include <exp_port.H>
+
+namespace mss
+{
+
+///
+/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc)
+/// @param[in] i_target the target
+/// @param[in,out] io_data contents of RECR register
+/// @return FAPI2_RC_SUCCESS if and only if ok
+/// @note mc_type::EXPLORER specialization
+///
+template< >
+fapi2::ReturnCode ecc_reg_settings_draminit_mc<mss::mc_type::EXPLORER>(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+    fapi2::buffer<uint64_t>& io_data )
+{
+    using TT = portTraits<mss::mc_type::EXPLORER>;
+    fapi2::buffer<uint64_t> l_ctcr_data;
+
+    // Explorer specific settings for RECR
+    io_data.setBit<TT::RECR_ENABLE_MPE_NOISE_WINDOW>();
+    io_data.setBit<TT::RECR_RETRY_UNMARKED_ERRORS>();
+    io_data.clearBit<TT::RECR_CFG_MAINT_USE_TIMERS>();
+
+    // Set up CTCR timers to 20x4^3 (1280 clock cycles; typical read latency is 120ish, so this is about 10x)
+    // This is a preliminary guess from the design team. Also enable UE lockout window
+    // CTCR -> 51A8E00000000000
+    FAPI_TRY( mss::getScom(i_target, TT::CTCR_REG, l_ctcr_data) );
+
+    l_ctcr_data.insertFromRight<TT::CTCR_MPE_TIMER, TT::CTCR_MPE_TIMER_LEN>(0b010100);
+    l_ctcr_data.insertFromRight<TT::CTCR_MPE_TIMEBASE, TT::CTCR_MPE_TIMEBASE_LEN>(0b011);
+    l_ctcr_data.insertFromRight<TT::CTCR_UE_TIMER, TT::CTCR_UE_TIMER_LEN>(0b010100);
+    l_ctcr_data.insertFromRight<TT::CTCR_UE_TIMEBASE, TT::CTCR_UE_TIMEBASE_LEN>(0b011);
+    l_ctcr_data.setBit<TT::CTCR_UE_LOCKOUT_ENABLE>();
+
+    FAPI_TRY( mss::putScom(i_target, TT::CTCR_REG, l_ctcr_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+}// mss

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H

@@ -76,6 +76,7 @@ class portTraits< mss::mc_type::EXPLORER >
         static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q;
         static constexpr uint64_t STR0Q_REG = EXPLR_SRQ_MBASTR0Q;
         static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR;
+        static constexpr uint64_t CTCR_REG = EXPLR_RDF_CTCR;
         static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q;
         static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0;
 
@@ -111,10 +112,25 @@ class portTraits< mss::mc_type::EXPLORER >
             BW_SNAPSHOT = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT,
             BW_SNAPSHOT_LEN = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN,
 
+            RECR_ENABLE_MPE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_MPE_NOISE_WINDOW,
             RECR_ENABLE_UE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW,
             RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION,
             RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION,
             RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN,
+            RECR_RETRY_UNMARKED_ERRORS = EXPLR_RDF_RECR_RETRY_UNMARKED_ERRORS,
+            RECR_CFG_MAINT_USE_TIMERS = EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS,
+            RECR_MBSECCQ_MAINT_NO_RETRY_UE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE,
+            RECR_MBSECCQ_MAINT_NO_RETRY_MPE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE,
+
+            CTCR_MPE_TIMER = EXPLR_RDF_CTCR_MPE_TIMER,
+            CTCR_MPE_TIMER_LEN = EXPLR_RDF_CTCR_MPE_TIMER_LEN,
+            CTCR_MPE_TIMEBASE = EXPLR_RDF_CTCR_MPE_TIMEBASE,
+            CTCR_MPE_TIMEBASE_LEN = EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN,
+            CTCR_UE_TIMER = EXPLR_RDF_CTCR_UE_TIMER,
+            CTCR_UE_TIMER_LEN = EXPLR_RDF_CTCR_UE_TIMER_LEN,
+            CTCR_UE_TIMEBASE = EXPLR_RDF_CTCR_UE_TIMEBASE,
+            CTCR_UE_TIMEBASE_LEN = EXPLR_RDF_CTCR_UE_TIMEBASE_LEN,
+            CTCR_UE_LOCKOUT_ENABLE = EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE,
 
             DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY,
             DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN,
@@ -187,7 +203,6 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-
 }// mss
 
 #endif

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C

@@ -64,6 +64,56 @@ fapi2::ReturnCode operation<mss::mc_type::EXPLORER>::multi_port_init_internal()
     return single_port_init();
 }
 
+///
+/// @brief Set up memory controller specific settings for pre-maint mode read
+/// @param[in] i_target the memory controller target
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note mc_type::EXPLORER specialization
+///
+template<>
+fapi2::ReturnCode pre_maint_read_settings<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
+        i_target )
+{
+    using TT = mss::portTraits<mss::mc_type::EXPLORER>;
+    fapi2::buffer<uint64_t> l_data;
+
+    // Set up Explorer specific settings
+    FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) );
+
+    l_data.setBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_UE>();
+    l_data.setBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_MPE>();
+
+    FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Set up memory controller specific settings for pre-scrub
+/// @param[in] i_target the memory controller target
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note mc_type::EXPLORER specialization
+///
+template<>
+fapi2::ReturnCode pre_scrub_settings<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
+        i_target )
+{
+    using TT = mss::portTraits<mss::mc_type::EXPLORER>;
+    fapi2::buffer<uint64_t> l_data;
+
+    // Set up Explorer specific settings
+    FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) );
+
+    l_data.clearBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_UE>();
+    l_data.clearBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_MPE>();
+
+    FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 } // namespace memdiags
 
 namespace exp

src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C

@@ -218,7 +218,7 @@ fapi2::ReturnCode self_refresh_exit_helper( const fapi2::Target<fapi2::TARGET_TY
         mss::mcbist::stop_conditions<> l_stop_conditions;
 
         // Read with targeted scrub
-        FAPI_TRY ( mss::memdiags::targeted_scrub(l_mcbist,
+        FAPI_TRY ( mss::memdiags::targeted_scrub<mss::mc_type::NIMBUS>(l_mcbist,
                    l_stop_conditions,
                    l_start,
                    l_end,

src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C

@@ -306,6 +306,21 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc)
+/// @param[in] i_target the target
+/// @param[in,out] io_data contents of RECR register
+/// @return FAPI2_RC_SUCCESS if and only if ok
+/// @note mc_type::NIMBUS specialization
+///
+template<>
+fapi2::ReturnCode ecc_reg_settings_draminit_mc<mss::mc_type::NIMBUS>(
+    const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+    fapi2::buffer<uint64_t>& io_data )
+{
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
 ///
 /// @brief Perform a repair for a single bad DQ bit in a nibble
 /// Specialization for TARGET_TYPE_DIMM

src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2019                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2020                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -50,6 +50,31 @@ namespace mss
 namespace memdiags
 {
 
+///
+/// @brief Set up memory controller specific settings for pre-maint mode read
+/// @param[in] i_target the memory controller target
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note mc_type::NIMBUS specialization
+///
+template<>
+fapi2::ReturnCode pre_maint_read_settings<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>&
+        i_target )
+{
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Set up memory controller specific settings for pre-scrub
+/// @param[in] i_target the memory controller target
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note mc_type::NIMBUS specialization
+///
+template<>
+fapi2::ReturnCode pre_scrub_settings<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target )
+{
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
 ///
 /// @brief Helper to encapsualte the setting of multi-port address configurations
 /// @return FAPI2_RC_SUCCESS iff ok

src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2020                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -140,10 +140,10 @@ extern "C"
             FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) );
 
             // Step Six: Setup Control Bit ECC
-            FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) );
+            FAPI_TRY( mss::enable_read_ecc<mss::mc_type::NIMBUS>(p), "%s Failed enable_read_ecc", mss::c_str(i_target) );
 
             // apply marks from MVPD
-            FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) );
+            FAPI_TRY( mss::apply_mark_store(p), "%s Failed apply_mark_store", mss::c_str(i_target) );
         }
 
         // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked.

src/import/generic/memory/lib/utils/mc/gen_mss_port.H

@@ -463,6 +463,19 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc)
+/// @tparam MC the memory controller type
+/// @tparam T the fapi2 target type of the target
+/// @tparam TT the class traits for the port
+/// @param[in] i_target the target
+/// @param[in,out] io_data contents of RECR register
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> >
+fapi2::ReturnCode ecc_reg_settings_draminit_mc( const fapi2::Target<T>& i_target,
+        fapi2::buffer<uint64_t>& io_data );
+
 ///
 /// @brief Enable Read ECC checking
 /// @tparam MC the memory controller type
@@ -471,9 +484,11 @@ fapi_try_exit:
 /// @param[in] i_target the target
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
-template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> >
+template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> >
 fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target )
 {
+    constexpr uint8_t RECR_MBSECCQ_DATA_INVERSION_NO_INVERSION = 0b00;
+    constexpr uint8_t RECR_MBSECCQ_DATA_INVERSION_INVERT_DATA_TOGGLE_CHECKS = 0b11;
     fapi2::buffer<uint64_t> l_data;
 
     uint8_t l_sim = 0;
@@ -487,13 +502,17 @@ fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target )
 
     // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything)
     // so we can't run with address checking. Disable address checking in sim.
-    l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1);
+    l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? mss::states::LOW : mss::states::HIGH);
 
-    // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS)   which stores data complemented
-    // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power)  but
+    // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented
+    // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but
     // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15
     // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC
-    l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11);
+    l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ?
+            RECR_MBSECCQ_DATA_INVERSION_NO_INVERSION :
+            RECR_MBSECCQ_DATA_INVERSION_INVERT_DATA_TOGGLE_CHECKS);
+
+    FAPI_TRY( ecc_reg_settings_draminit_mc<MC>(i_target, l_data) );
 
     // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE
     // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus.