p9_sbe_select_ex Level 2 update

- add PFET Delay settings for booting Quads/Cores for istep 4
- Delays controled the -DPRODUCT_DEFAULT_PFET_DELAY compile switch
   - if not defined (aka simulation), delays only 1 cycle between steps
     (on or off)
   - if defined, fixed delays based on the fastest nest times to meet
      minimum times for hardware (turn on);  turn off is fast
- Backed out the vector use reduction as this presented SBE platform
problems.  Those will be addressed in RTC 151413
- Per discussion to have ALL good core/cache and EX Multicast groups
setup in p9_sbe_chiplet_reset, redid this procedure to only REMOVE
chiplets from groups 3, 4, 5, and 6 in single mode (the default) so
as to leave only one core n group 3 with the associated EQ in group 4
and the assoicated EX in either group 5 or 6 depending on even or odd
EX number.  If ALL mode (controlled by an attribute), no MC groups are
modified.
- Vector removal was addressed by removing some error checking for the
sake of SBE code space.
- Added default setting of QSSR that all L2s and Quads are stopped

Change-Id: I650ab91b72cce86d9b7f319e988cccc72a691abd
RTC: 151360
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23138
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36094
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H

@@ -48,7 +48,71 @@ enum powerOperation_t
     POWER_ON_VDD  = 0x1,
     POWER_OFF_VDD = 0xFE
 };
-}
+
+
+
+// For SBE, the initial power-on times are not overly time critical so they are
+// hardcoded for the delay necessary when running with the fastest nest (2.4GHz).
+// When these same values are used with slower nest frequencies, the delays will
+// get longer (more conservative).
+//
+// For istep 15, the delay settings are computed based on the setting of
+// ATTR_FREQ_PB
+//
+// pfet_delay = (1/nest_frequency_mhz)*1000*4 (PPM clock period in ns) *
+//               2^(15-pfet_delay_value).
+//
+// or
+//
+//                                                pfet_delay
+// 2^(15-pfet_delay_value) =           ------------------------------
+//                                     (1/nest_frequency_mhz)*1000*4
+//
+//                                     pfet_delay * nest_frequency_mhz
+// 2^(15-pfet_delay_value  =           ------------------------------
+//                                                1000*4
+//
+//                                    ( pfet_delay * nest_frequency_mhz)
+// 15-pfet_delay_value     =      log2(  ------------------------------)
+//                                    (             1000*4             )
+//
+//                                    ( pfet_delay * nest_frequency_mhz)
+// pfet_delay_value        = 15 - log2(  ------------------------------)
+//                                    (             1000*4             )
+//
+//            ( pfet_delay * nest_frequency_mhz)
+// logexp   = (  ------------------------------)
+//            (             1000*4             )
+//
+//          = pfet_delay * nest_frequency_mhz / (1000 * 4)
+//          = pfet_delay * (nest_frequency_mhz / (1000 * 4))
+//          = pfet_delay * (2400 / (1000 * 4))
+//          = pfet_delay * (.6)
+//
+// For core delay of 250ns per step, logexp = 250 * .6 = 150
+//   --> log2(150) = 8 (rounded up to next integer)
+//  -- > pfet_delay_value = 15 - 8 = 7
+//
+// For EQ delay of 500ns per step, logexp = 500 * .6 = 300
+//   --> log2(150) = 9 (rounded up to next integer)
+//  -- > pfet_delay_value = 15 - 9 = 6
+
+
+enum pfetDelays
+{
+    PFET_DELAY_POWERDOWN_EQ     = 0x1,
+    PFET_DELAY_POWERDOWN_CORE   = 0x1,
+#ifndef PRODUCT_DEFAULT_PFET_DELAYS
+    PFET_DELAY_POWERUP_EQ       = 0x1,
+    PFET_DELAY_POWERUP_CORE     = 0x1
+#else
+    PFET_DELAY_POWERUP_EQ       = 0x6,
+    PFET_DELAY_POWERUP_CORE     = 0x7
+#endif
+};
+
+
+} // namespace
 
 /// @typedef p9_common_poweronoff_FP_t
 /// function pointer typedef definition for HWP call support