Added MRS attributes and MRS data handling for Explorer

Change-Id: I4050965a6195217eef15325719b6a01935cc1bbb
Original-Change-Id: Ia5db0e40c9d0f3bdcc590a7803471f7dc0fdcd77
git-coreq:hostboot:Ia5db0e40c9d0f3bdcc590a7803471f7dc0fdcd77
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89850
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/95191
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/ddr4/exp_mrs00.C

@@ -22,3 +22,80 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_mrs00.C
+/// @brief Run and manage the DDR4 MRS00 loading
+///
+// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/shared/exp_defaults.H>
+#include <lib/dimm/exp_mrs_traits.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H>
+#include <generic/memory/lib/dimm/ddr4/mrs00.H>
+
+namespace mss
+{
+
+namespace ddr4
+{
+
+///
+/// @brief mrs0_data ctor
+/// @param[in] a fapi2::TARGET_TYPE_DIMM target
+/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
+/// @note Burst Length will always be set to fixed x8 (0)
+/// @note Burst Chop (x4) is not supported
+///
+template<>
+mrs00_data<mss::mc_type::EXPLORER>::mrs00_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        fapi2::ReturnCode& o_rc ):
+    iv_burst_length(0),
+    iv_read_burst_type(fapi2::ENUM_ATTR_MSS_EXP_RESP_DRAM_RBT_SEQUENTIAL),
+    iv_dll_reset(fapi2::ENUM_ATTR_MSS_EXP_RESP_DRAM_DLL_RESET_NO),
+    iv_test_mode(fapi2::ENUM_ATTR_MSS_EXP_RESP_DRAM_TM_NORMAL),
+    iv_write_recovery(0),
+    iv_cas_latency(0)
+{
+    const auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
+
+    FAPI_TRY( mss::attr::get_exp_resp_dram_rbt(l_port_target, iv_read_burst_type), "Error in mrs00_data()" );
+    FAPI_TRY( mss::attr::get_dram_cl(l_port_target, iv_cas_latency), "Error in mrs00_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_dll_reset(l_port_target, iv_dll_reset), "Error in mrs00_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_tm(l_port_target, iv_test_mode), "Error in mrs00_data()" );
+    FAPI_TRY( mss::attr::get_dram_twr(l_port_target, iv_write_recovery), "Error in mrs00_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_burst_length(l_port_target, iv_burst_length), "Error in mrs00_data()" );
+
+    FAPI_INF("%s MR0 Attributes: BL: 0x%x, RBT: 0x%x, CL: 0x%x, TM: 0x%x, DLL_RESET: 0x%x, WR: 0x%x",
+             mss::c_str(i_target), iv_burst_length, iv_read_burst_type, iv_cas_latency, iv_test_mode, iv_dll_reset,
+             iv_write_recovery);
+
+    o_rc = fapi2::FAPI2_RC_SUCCESS;
+    return;
+fapi_try_exit:
+    o_rc = fapi2::current_err;
+    FAPI_ERR("%s unable to get attributes for mrs00", mss::c_str(i_target));
+    return;
+}
+
+template<>
+fapi2::ReturnCode (*mrs00_data<mss::mc_type::EXPLORER>::make_ccs_instruction)(const
+        fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const mrs00_data<mss::mc_type::EXPLORER>& i_data,
+        ccs::instruction_t& io_inst,
+        const uint64_t i_rank) = &mrs00;
+
+template<>
+fapi2::ReturnCode (*mrs00_data<mss::mc_type::EXPLORER>::decode)(const ccs::instruction_t& i_inst,
+        const uint64_t i_rank) = &mrs00_decode;
+
+} // ns ddr4
+
+} // ns mss

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/ddr4/exp_mrs01.C

@@ -22,3 +22,108 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_mrs01.C
+/// @brief Run and manage the DDR4 MRS01 loading
+///
+// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/shared/exp_defaults.H>
+#include <lib/dimm/exp_mrs_traits.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H>
+#include <generic/memory/lib/dimm/ddr4/mrs01.H>
+
+namespace mss
+{
+
+namespace ddr4
+{
+
+///
+/// @brief Helper function to decode ODIC to the MRS value - explorer specialization
+/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[in] i_odic_value the value to be decoded for ODIC
+/// @param[out] o_odic_decode the MRS decoded value for ODIC
+/// @return FAPI2_RC_SUCCESS iff OK
+///
+template<>
+fapi2::ReturnCode odic_helper<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const uint8_t i_odic_value,
+        fapi2::buffer<uint8_t>& o_odic_decode)
+{
+    constexpr uint8_t MAX_ODIC_VALUE = 0b01;
+    FAPI_ASSERT( i_odic_value < MAX_ODIC_VALUE,
+                 fapi2::MSS_BAD_MR_PARAMETER()
+                 .set_MR_NUMBER(1)
+                 .set_PARAMETER(OUTPUT_IMPEDANCE)
+                 .set_PARAMETER_VALUE(i_odic_value)
+                 .set_DIMM_IN_ERROR(i_target),
+                 "Bad value for output driver impedance: %d (%s)",
+                 i_odic_value,
+                 mss::c_str(i_target));
+
+    o_odic_decode = i_odic_value;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief mrs01_data ctor
+/// @param[in] a fapi2::TARGET_TYPE_DIMM target
+/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
+///
+template<>
+mrs01_data<mss::mc_type::EXPLORER>::mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        fapi2::ReturnCode& o_rc ):
+    iv_dll_enable(fapi2::ENUM_ATTR_MSS_EXP_RESP_DRAM_DLL_ENABLE_ENABLE),
+    iv_additive_latency(0),
+    iv_wl_enable(0),
+    iv_tdqs(0),
+    iv_qoff(0)
+{
+    const auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
+
+    FAPI_TRY( mss::attr::get_exp_resp_dram_dll_enable(l_port_target, iv_dll_enable),
+              "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_odic(i_target, iv_odic), "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_al(l_port_target, iv_additive_latency), "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_wr_lvl_enable(l_port_target, iv_wl_enable),
+              "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_rtt_nom(i_target, iv_rtt_nom), "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_tdqs(l_port_target, iv_tdqs), "Error in mrs01_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_output_buffer(l_port_target, iv_qoff), "Error in mrs01_data()" );
+
+    o_rc = fapi2::FAPI2_RC_SUCCESS;
+    return;
+
+fapi_try_exit:
+    o_rc = fapi2::current_err;
+    FAPI_ERR("%s unable to get attributes for mrs01");
+    return;
+}
+
+template<>
+fapi2::ReturnCode (*mrs01_data<mss::mc_type::EXPLORER>::make_ccs_instruction)(const
+        fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const mrs01_data<mss::mc_type::EXPLORER>& i_data,
+        ccs::instruction_t& io_inst,
+        const uint64_t i_rank) = &mrs01;
+
+template<>
+fapi2::ReturnCode (*mrs01_data<mss::mc_type::EXPLORER>::decode)(const ccs::instruction_t& i_inst,
+        const uint64_t i_rank) = &mrs01_decode;
+
+} // ns ddr4
+
+} // ns mss

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/ddr4/exp_mrs02.C

@@ -22,3 +22,71 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_mrs02.C
+/// @brief Run and manage the DDR4 MRS02 loading
+///
+// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/shared/exp_defaults.H>
+#include <lib/dimm/exp_mrs_traits.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H>
+#include <generic/memory/lib/dimm/ddr4/mrs02.H>
+#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
+
+namespace mss
+{
+
+namespace ddr4
+{
+
+///
+/// @brief mrs02_data ctor
+/// @param[in] a fapi2::TARGET_TYPE_DIMM target
+/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
+///
+template<>
+mrs02_data<mss::mc_type::EXPLORER>::mrs02_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        fapi2::ReturnCode& o_rc ):
+    iv_lpasr(0),
+    iv_cwl(0),
+    iv_write_crc(0)
+{
+    const auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
+
+    FAPI_TRY( mss::attr::get_exp_resp_dram_lpasr(l_port_target, iv_lpasr), "Error in mrs02_data()" );
+    FAPI_TRY( mss::attr::get_dram_cwl(l_port_target, iv_cwl), "Error in mrs02_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_dram_rtt_wr(i_target, iv_dram_rtt_wr), "Error in mrs02_data()" );
+    FAPI_TRY( mss::attr::get_mrw_dram_write_crc(iv_write_crc), "Error in mrs02_data()" );
+
+    o_rc = fapi2::FAPI2_RC_SUCCESS;
+    return;
+
+fapi_try_exit:
+    o_rc = fapi2::current_err;
+    FAPI_ERR("%s unable to get attributes for mrs02", mss::c_str(i_target));
+    return;
+}
+
+template<>
+fapi2::ReturnCode (*mrs02_data<mss::mc_type::EXPLORER>::make_ccs_instruction)(const
+        fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const mrs02_data<mss::mc_type::EXPLORER>& i_data,
+        ccs::instruction_t& io_inst,
+        const uint64_t i_rank) = &mrs02;
+
+template<>
+fapi2::ReturnCode (*mrs02_data<mss::mc_type::EXPLORER>::decode)(const ccs::instruction_t& i_inst,
+        const uint64_t i_rank) = &mrs02_decode;
+
+} // ns ddr4
+
+} // ns mss

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/ddr4/exp_mrs03.C

@@ -22,3 +22,115 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_mrs03.C
+/// @brief Run and manage mrs03
+///
+// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/shared/exp_defaults.H>
+#include <lib/dimm/exp_mrs_traits.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H>
+#include <generic/memory/lib/dimm/ddr4/mrs03.H>
+#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
+
+namespace mss
+{
+
+namespace ddr4
+{
+
+///
+/// @brief Helper function to decode CRC WR latency to the MRS value - explorer specialization
+/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[in] i_value the value to be decoded
+/// @param[out] o_decode the MRS decoded value
+/// @return FAPI2_RC_SUCCESS iff OK
+///
+template<>
+fapi2::ReturnCode crc_wr_latency_helper<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const uint8_t i_value,
+        fapi2::buffer<uint8_t>& o_decode)
+{
+    constexpr uint8_t MAX_VALUE = 0b10;
+    FAPI_ASSERT( i_value < MAX_VALUE,
+                 fapi2::MSS_BAD_MR_PARAMETER()
+                 .set_MR_NUMBER(3)
+                 .set_PARAMETER(OUTPUT_IMPEDANCE)
+                 .set_PARAMETER_VALUE(i_value)
+                 .set_DIMM_IN_ERROR(i_target),
+                 "Bad value for Write CMD Latency: %d (%s)",
+                 i_value,
+                 mss::c_str(i_target));
+
+    o_decode = i_value;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief mrs03_data ctor
+/// @param[in] a fapi2::TARGET_TYPE_DIMM target
+/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok
+///
+template<>
+mrs03_data<mss::mc_type::EXPLORER>::mrs03_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        fapi2::ReturnCode& o_rc ):
+    iv_mpr_mode(fapi2::ENUM_ATTR_MSS_EXP_RESP_MPR_MODE_DISABLE),
+    iv_mpr_page(fapi2::ENUM_ATTR_MSS_EXP_RESP_MPR_PAGE_PG0),
+    iv_geardown(0),
+    iv_pda(fapi2::ENUM_ATTR_MSS_EXP_RESP_PER_DRAM_ACCESS_DISABLE),
+    iv_crc_wr_latency(0),
+    iv_temp_readout(fapi2::ENUM_ATTR_MSS_EXP_RESP_TEMP_READOUT_DISABLE),
+    iv_fine_refresh(0),
+    iv_read_format(fapi2::ENUM_ATTR_MSS_EXP_RESP_MPR_RD_FORMAT_SERIAL)
+{
+    const auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
+
+    FAPI_TRY( mss::attr::get_exp_resp_mpr_mode(l_port_target, iv_mpr_mode), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_mpr_page(l_port_target, iv_mpr_page), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_geardown_mode(l_port_target, iv_geardown), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_per_dram_access(l_port_target, iv_pda), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_temp_readout(l_port_target, iv_temp_readout), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_mrw_fine_refresh_mode(iv_fine_refresh), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_crc_wr_latency(l_port_target, iv_crc_wr_latency), "Error in mrs03_data()" );
+    FAPI_TRY( mss::attr::get_exp_resp_mpr_rd_format(l_port_target, iv_read_format), "Error in mrs03_data()" );
+
+    FAPI_INF("%s MR3 attributes: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, "
+             "TEMP: 0x%x FR: 0x%x, CRC_WL: 0x%x, RF: 0x%x",
+             mss::c_str(i_target), iv_mpr_mode, iv_mpr_page, iv_geardown, iv_pda,
+             iv_temp_readout, iv_fine_refresh, iv_crc_wr_latency, iv_read_format);
+
+    o_rc = fapi2::FAPI2_RC_SUCCESS;
+    return;
+
+fapi_try_exit:
+    o_rc = fapi2::current_err;
+    FAPI_ERR("%s unable to get attributes for mrs03");
+    return;
+}
+
+template<>
+fapi2::ReturnCode (*mrs03_data<mss::mc_type::EXPLORER>::make_ccs_instruction)(const
+        fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        const mrs03_data<mss::mc_type::EXPLORER>& i_data,
+        ccs::instruction_t& io_inst,
+        const uint64_t i_rank) = &mrs03;
+
+template<>
+fapi2::ReturnCode (*mrs03_data<mss::mc_type::EXPLORER>::decode)(const ccs::instruction_t& i_inst,
+        const uint64_t i_rank) = &mrs03_decode;
+
+} // ns ddr4
+} // ns mss