STOP API: API conditionally supports 255 SCOM restore entries for eac…

…h quad.

This is first of the series of commits intended for incorporating
new mechanisms for SCOM restore. STOP API looks for a specific
version in QPMR header of HOMER. If version is greater than 2, it allows
 - 255 SCOM Restore entries per quad
 - doesn't divide quad restore region in to L2, L3 and EQ sub-region
If version is less than or equal to 2, API provideis legacy functionality.
Key_Cronus_Test=PM_REGRESS

RTC: 188827
Change-Id: Iac6ee94619302f745fee0c77acc168eaba04c3da
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56385
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56390
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H

@@ -173,6 +173,7 @@ HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE,           0x58)
 HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE,           0x5C)
 HCD_CONST(QPMR_SGPE_BOOT_PROG_CODE,             0x60)
 HCD_CONST(QPMR_SGPE_IMAGE_SIZE,                 0x64)
+HCD_CONST(QPMR_QUAD_MAX_SCOM_ENTRY_BYTE,        0x68)
 
 /// SGPE Boot
 
@@ -289,6 +290,7 @@ HCD_CONST(QUAD_SCOM_RESTORE_SIZE_PER_QUAD,
           (SCOM_RESTORE_ENTRY_SIZE* QUAD_SCOM_RESTORE_REGS_PER_QUAD))
 
 HCD_CONST(QUAD_SCOM_RESTORE_SIZE_TOTAL,         (6 * ONE_KB)) //rounded to 6KB
+HCD_CONST(LEGACY_SCOM_RESTORE_VER,              0x02)
 //FFDC Region
 HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000)    //Offset wrt to QPMR base
 HCD_CONST(FFDC_REGION_SIZE,  (80 * ONE_KB))
@@ -321,6 +323,7 @@ HCD_CONST(CPMR_CORE_SCOM_RESTORE_OFFSET_BYTE,   0x40)
 HCD_CONST(CPMR_CORE_SCOM_RESTORE_LENGTH_BYTE,   0x44)
 HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE,        0x48)
 HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE,        0x4C)
+HCD_CONST(CPMR_MAX_SCOM_REST_PER_CORE_BYTE,     0x50)
 
 /// Self Restore
 

src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H

@@ -103,6 +103,7 @@ HCD_HDR_UINT32( stopFfdcOffset, 0);
 HCD_HDR_UINT32( stopFfdcLength, 0);
 HCD_HDR_UINT32( sgpeBootProgCode, 0 );
 HCD_HDR_UINT32( sgpeSramImageSize, 0 );
+HCD_HDR_UINT32( maxQuadScomRestoreEntry, 0 );
 HCD_HDR_PAD(512);
 #ifdef __ASSEMBLER__
 .endm
@@ -145,6 +146,9 @@ HCD_HDR_UINT32( coreSpecRingOffset, 0);
 HCD_HDR_UINT32( coreSpecRingLength, 0);
 HCD_HDR_UINT32( coreScomOffset, 0);
 HCD_HDR_UINT32( coreScomLength, 0);
+HCD_HDR_UINT32( coreSelfRestoreOffset, 0);
+HCD_HDR_UINT32( coreSelfRestoreLength, 0);
+HCD_HDR_UINT32( coreMaxScomEntry, 0);
 HCD_HDR_PAD(CPMR_HEADER_SIZE);
 #ifdef __ASSEMBLER__
 .endm

src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C

@@ -1186,6 +1186,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer )
     pCpmrHdr->cmeImgLength              =   pCmeHdr->g_cme_hcode_length;// already swizzled
     pCpmrHdr->coreScomOffset            =   SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_CPMR_OFFSET);
     pCpmrHdr->coreScomLength            =   SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL);
+    pCpmrHdr->coreMaxScomEntry          =   SWIZZLE_4_BYTE(MAX_CORE_SCOM_ENTRIES);
 
     if( pCmeHdr->g_cme_common_ring_length )
     {
@@ -1249,6 +1250,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer )
     FAPI_INF(" CSR Length       : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength));
     FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset));
     FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength ));
+    FAPI_INF(" Max SCOM Entries : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreMaxScomEntry));
     FAPI_INF("==================================CPMR Ends=====================================");
 
     FAPI_INF("<< updateCpmrCmeRegion");
@@ -1298,6 +1300,8 @@ void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrH
                                    SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength) +
                                    SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength);
 
+    io_qpmrHdr.maxQuadScomRestoreEntry  =   SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_REGS_PER_QUAD - 1);
+
     io_qpmrHdr.sgpeSramImageSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeSramImageSize);
     memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) );
     pSgpeHdr->g_sgpe_scom_mem_offset        =   SWIZZLE_4_BYTE(QPMR_HOMER_OFFSET + QUAD_SCOM_RESTORE_QPMR_OFFSET );
@@ -1319,6 +1323,7 @@ void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrH
     FAPI_INF("  Quad SCOM Offset        : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomOffset) );
     FAPI_INF("  Quad SCOM Length        : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomLength) );
     FAPI_DBG("  SGPE SRAM Img Size      : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->sgpeSramImageSize ) );
+    FAPI_DBG("  Max SCOM Rest Entry     : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->maxQuadScomRestoreEntry ) );
     FAPI_DBG("==============================QPMR Ends==============================");
 
     FAPI_DBG("===========================SGPE Image Hdr=============================");