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Axone Xbus Linearity
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Change-Id: I7890146ba7e05197910bdbe77d19f221b7b5b912
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76460
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76472
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@steffenchris @crgeddes
steffenchris authored and crgeddes committed Apr 30, 2019
1 parent 19fde64 commit d91209c
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Showing 5 changed files with 149 additions and 15 deletions.
35 changes: 31 additions & 4 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
View file
Expand Up @@ -43,10 +43,13 @@ constexpr uint64_t literal_0b0000011 = 0b0000011;
constexpr uint64_t literal_0b000000 = 0b000000;
constexpr uint64_t literal_0b100111 = 0b100111;
constexpr uint64_t literal_0b1010 = 0b1010;
constexpr uint64_t literal_0b00 = 0b00;
constexpr uint64_t literal_0b01 = 0b01;
constexpr uint64_t literal_0b11 = 0b11;
constexpr uint64_t literal_0b01010000 = 0b01010000;
constexpr uint64_t literal_0b01011100 = 0b01011100;
constexpr uint64_t literal_0b01100110 = 0b01100110;
constexpr uint64_t literal_0b00110111 = 0b00110111;
constexpr uint64_t literal_0b00111101 = 0b00111101;
constexpr uint64_t literal_0b01000100 = 0b01000100;
constexpr uint64_t literal_0b0010000 = 0b0010000;
Expand All @@ -61,7 +64,6 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000;
constexpr uint64_t literal_0b01111111 = 0b01111111;
constexpr uint64_t literal_0b10 = 0b10;
constexpr uint64_t literal_0b1100 = 0b1100;
constexpr uint64_t literal_0b00 = 0b00;
constexpr uint64_t literal_0b01110 = 0b01110;

fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
Expand All @@ -80,6 +82,9 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_CHAN_EQ, TGT0, l_TGT0_ATTR_IO_XBUS_CHAN_EQ));
fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297));
fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND_Type l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND, TGT2,
l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND));
fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE));
uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1);
Expand Down Expand Up @@ -3213,7 +3218,15 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x8008c00006010c3full, l_scom_buffer ));

l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 );
}
else if (( true ))
{
l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
}

constexpr auto l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0;
l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF );
l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 );
Expand All @@ -3238,7 +3251,11 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x8008d00006010c3full, l_scom_buffer ));

if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 );
}
else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
{
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
}
Expand All @@ -3247,7 +3264,11 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 );
}

if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 );
}
else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
{
l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
}
Expand Down Expand Up @@ -3377,6 +3398,12 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&

constexpr auto l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0;
l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF );

if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 );
}

FAPI_TRY(fapi2::putScom(TGT0, 0x800b800006010c3full, l_scom_buffer));
}
{
Expand Down
40 changes: 36 additions & 4 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
View file
Expand Up @@ -44,10 +44,13 @@ constexpr uint64_t literal_0b000000 = 0b000000;
constexpr uint64_t literal_0b100111 = 0b100111;
constexpr uint64_t literal_0b000001 = 0b000001;
constexpr uint64_t literal_0b1010 = 0b1010;
constexpr uint64_t literal_0b00 = 0b00;
constexpr uint64_t literal_0b01 = 0b01;
constexpr uint64_t literal_0b11 = 0b11;
constexpr uint64_t literal_0b01010000 = 0b01010000;
constexpr uint64_t literal_0b01011100 = 0b01011100;
constexpr uint64_t literal_0b01100110 = 0b01100110;
constexpr uint64_t literal_0b00110111 = 0b00110111;
constexpr uint64_t literal_0b00111101 = 0b00111101;
constexpr uint64_t literal_0b01000100 = 0b01000100;
constexpr uint64_t literal_0b0010000 = 0b0010000;
Expand All @@ -62,7 +65,6 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000;
constexpr uint64_t literal_0b01111111 = 0b01111111;
constexpr uint64_t literal_0b10 = 0b10;
constexpr uint64_t literal_0b1100 = 0b1100;
constexpr uint64_t literal_0b00 = 0b00;
constexpr uint64_t literal_0b01110 = 0b01110;

fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
Expand All @@ -81,6 +83,9 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_CHAN_EQ, TGT0, l_TGT0_ATTR_IO_XBUS_CHAN_EQ));
fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297));
fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND_Type l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND, TGT2,
l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND));
fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE));
uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1);
Expand Down Expand Up @@ -3211,10 +3216,23 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1010 );
FAPI_TRY(fapi2::putScom(TGT0, 0x8008402006010c3full, l_scom_buffer));
}
{
FAPI_TRY(fapi2::getScom( TGT0, 0x8008c00006010c3full, l_scom_buffer ));

if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 );
}
else if (( true ))
{
l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
}

FAPI_TRY(fapi2::putScom(TGT0, 0x8008c00006010c3full, l_scom_buffer));
}
{
FAPI_TRY(fapi2::getScom( TGT0, 0x8008c02006010c3full, l_scom_buffer ));

l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
constexpr auto l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0;
l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF );
l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 );
Expand All @@ -3239,7 +3257,11 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
{
FAPI_TRY(fapi2::getScom( TGT0, 0x8008d02006010c3full, l_scom_buffer ));

if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 );
}
else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
{
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
}
Expand All @@ -3248,7 +3270,11 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 );
}

if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 );
}
else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
{
l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
}
Expand Down Expand Up @@ -3378,6 +3404,12 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&

constexpr auto l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0;
l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF );

if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)
{
l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 );
}

FAPI_TRY(fapi2::putScom(TGT0, 0x800b802006010c3full, l_scom_buffer));
}
{
Expand Down
15 changes: 8 additions & 7 deletions src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
View file
Expand Up @@ -193,6 +193,14 @@
#define EDIP_RX_BER_TIMEOUT 0x800888000000003f, 56, 4 // rx_ber_timeout, used for when making bit error measurements with a servo op (see workbook table 4.10 for timer settings)
#define EDIP_RX_CTL_MODE16_EO_PG 0x800888000000003f, 48, 16 // register -- description
#define EDIP_CHAN_FAIL_MASK 0x0000000000000020, 15, 8 // scom mode reg spares.
#define EDIP_RX_PG_SPARE_MODE_0 0x800800000000003f, 48, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_1 0x800800000000003f, 49, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_2 0x800800000000003f, 50, 1 // per-group spare mode latch.
#define EDIP_RX_RC_ENABLE_CM_FINE_CAL 0x8008b8000000003f, 56, 1 // rx recalibration common mode fine calibration enable
#define EDIP_RX_EO_ENABLE_DAC_H1_CAL 0x8008b0000000003f, 50, 1 // rx eye optimization h! dac calibration to reference
#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL 0x8008b0000000003f, 61, 1 // rx eye optimization h! dac to amplitude dac cross-calibration
#define EDIP_RX_A_INTEG_COARSE_GAIN 0x800028000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments.



#define EDI_RX_WTM_STATE 0x800950000000003f, 48, 5 // main wiretest state machine current state (rjr)): \r\n\tx00: idle \r\n\tx01: drv data wt \r\n\tx02: drv clock wt \r\n\tx03: drv data 0 \r\n\tx04: drv clock 0 \r\n\tx05: rx wt \r\n\tx06: wait all ones \r\n\tx07: reset pll \r\n\tx08: wait pll \r\n\tx09: drive clock \r\n\tx0a: drive data 1 \r\n\tx0b: wait all zeroes \r\n\tx0c: drive data 0 \r\n\tx0d: done \r\n\tx0e: unused \r\n\tx0f: unused \r\n\tx10: wait prev done \r\n\tx11: drv prev done \r\n\tx12: drv all done \r\n\tx13: wait all done \r\n\tx14: init tx fifo \r\n\tx15: unused \r\n\tx16: unused \r\n\tx17: unused \r\n\tx18: set c & d dr strength \r\n\tx19: set data only dr strength \r\n\tx1a: clock fail \r\n\tx1b: all bad lanes \r\n\tx1c: wt timeout fail \r\n\tx1d: pll/dll fail \r\n\tx1e: all ones fail \r\n\tx1f: all zeroes fail \r\n\trjr
Expand Down Expand Up @@ -2496,7 +2504,6 @@
#define EDIP_RX_A_OFFSET_O0 0x800020000000003f, 48, 7 // this is the vertical offset of the odd low threshold sampling latch.
#define EDIP_RX_A_OFFSET_O1 0x800020000000003f, 56, 7 // this is the vertical offset of the odd high threshold sampling latch.
#define EDIP_RX_DAC_CNTL4_EO_PL 0x800020000000003f, 48, 16 // register -- description
#define EDIP_RX_A_INTEG_COARSE_GAIN 0x800028000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments.
#define EDIP_RX_A_EVEN_INTEG_FINE_GAIN 0x800028000000003f, 52, 5 // this is integrator gain control used in making common mode adjustments.
#define EDIP_RX_A_ODD_INTEG_FINE_GAIN 0x800028000000003f, 57, 5 // this is integrator gain control used in making common mode adjustments.
#define EDIP_RX_DAC_CNTL5_EO_PL 0x800028000000003f, 48, 16 // register -- description
Expand Down Expand Up @@ -2703,9 +2710,6 @@
#define EDIP_RX_A_PATH_OFF_EVEN 0x800398000000003f, 48, 6 // eye opt a bank even path offset
#define EDIP_RX_A_PATH_OFF_ODD 0x800398000000003f, 54, 6 // eye opt a bank odd path offset
#define EDIP_RX_WORK_STAT3_EO_PL 0x800398000000003f, 48, 16 // register -- description
#define EDIP_RX_PG_SPARE_MODE_0 0x800800000000003f, 48, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_1 0x800800000000003f, 49, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_2 0x800800000000003f, 50, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_3 0x800800000000003f, 51, 1 // per-group spare mode latch.
#define EDIP_RX_PG_SPARE_MODE_4 0x800800000000003f, 52, 1 // chicken switch for hw219893. fix is to prevent the rx_sls_hndshk_state sm and the rx_dyn_recal_hndshk_state sm from ever being allowed to run at the same time. setting the cs turns this feature off.
#define EDIP_RX_SPARE_MODE_PG 0x800800000000003f, 48, 16 // register -- description
Expand Down Expand Up @@ -2803,7 +2807,6 @@
#define EDIP_RX_EO_STEP_CNTL_EDI_ALIAS 0x8008b0000000003f, 48, 16 // rx eye optimization step control edi alias
#define EDIP_RX_EO_ENABLE_INTEG_LATCH_OFFSET_CAL 0x8008b0000000003f, 48, 1 // rx eye optimization latch offset adjustment enable with integrator-based disable
#define EDIP_RX_EO_ENABLE_CTLE_COARSE_CAL 0x8008b0000000003f, 49, 1 // rx eye optimization coarse ctle/peakin enable
#define EDIP_RX_EO_ENABLE_DAC_H1_CAL 0x8008b0000000003f, 50, 1 // rx eye optimization h! dac calibration to reference
#define EDIP_RX_EO_ENABLE_VGA_CAL 0x8008b0000000003f, 51, 1 // rx eye optimization vga gainand offset adjust enable
#define EDIP_RX_EO_ENABLE_DFE_H1_CAL 0x8008b0000000003f, 52, 1 // rx eye optimization dfe h1 adjust enable
#define EDIP_RX_EO_ENABLE_H1AP_TWEAK 0x8008b0000000003f, 53, 1 // rx eye optimization h1/an pr adjust enable
Expand All @@ -2814,7 +2817,6 @@
#define EDIP_RX_EO_ENABLE_RESULT_CHECK 0x8008b0000000003f, 58, 1 // rx eye optimization final results check enable
#define EDIP_RX_EO_ENABLE_CTLE_EDGE_TRACK_ONLY 0x8008b0000000003f, 59, 1 // rx eye optimization ctle/peakin enable with edge tracking only
#define EDIP_RX_EO_ENABLE_DFE_H2_H12_CAL 0x8008b0000000003f, 60, 1 // rx eye optimization dfe h2 to h12 calibration enable
#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL 0x8008b0000000003f, 61, 1 // rx eye optimization h! dac to amplitude dac cross-calibration
#define EDIP_RX_EO_ENABLE_FINAL_L2U_ADJ 0x8008b0000000003f, 62, 1 // rx eye optimization final rx fifo load-to-unload delay adjustment enable
#define EDIP_RX_EO_ENABLE_DONE_SIGNALING 0x8008b0000000003f, 63, 1 // rx eye optimization eye opt done signaling enable
#define EDIP_RX_CTL_MODE21_EO_PG 0x8008b0000000003f, 48, 16 // register -- description
Expand All @@ -2827,7 +2829,6 @@
#define EDIP_RX_RC_ENABLE_H1AP_TWEAK 0x8008b8000000003f, 53, 1 // rx recalibration h1/an pr adjust enable
#define EDIP_RX_RC_ENABLE_DDC 0x8008b8000000003f, 54, 1 // rx recalibration dynamic data centering enable
#define EDIP_RX_RC_ENABLE_CM_COARSE_CAL 0x8008b8000000003f, 55, 1 // rx recalibration common mode coarse calibration enable
#define EDIP_RX_RC_ENABLE_CM_FINE_CAL 0x8008b8000000003f, 56, 1 // rx recalibration common mode fine calibration enable
#define EDIP_RX_RC_ENABLE_BER_TEST 0x8008b8000000003f, 57, 1 // rx recalibration unsupported, leave at 0. bit error rate test enable
#define EDIP_RX_RC_ENABLE_RESULT_CHECK 0x8008b8000000003f, 58, 1 // rx recalibration unsupported, leave at 0. final results check enable
#define EDIP_RX_RC_ENABLE_CTLE_EDGE_TRACK_ONLY 0x8008b8000000003f, 59, 1 // rx recalibration ctle/peaking enable with edge tracking only
Expand Down

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