Add new MSS attributes for Axone

  ATTR_MEM_MRW_IS_PLANAR
  ATTR_MEM_EFF_DIMM_SPARE
  ATTR_MEM_VPD_DQ_MAP

Change-Id: I1e63f4d6113f4adbcd7f149f00c14bb023115611
Original-Change-Id: I36915bf7aa8c6fffc3e8b27aea595d9feb1760dc
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69903
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71934
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml

@@ -646,6 +646,21 @@
         <mssAccessorName>dimm_size</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MEM_EFF_DIMM_SPARE</id>
+        <targetType>TARGET_TYPE_MEM_PORT</targetType>
+        <description>
+            Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg.
+            Array indexes are [DIMM][RANK]
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum>
+        <writeable/>
+        <array> 2 4</array>
+        <mssAccessorName>dimm_spare</mssAccessorName>
+    </attribute>
+
     <attribute>
         <id>ATTR_MEM_EFF_DRAM_CL</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>