Call p9a_throttle_sync inside mss_scominit

We need to setup the memory throttles for worstcase mode for a portion of the boot before we have the real values later in mss_thermal_init. Changes to IPL flow - 13.8 mss_scominit - exp_scominit() - p9a_throttle_sync() <<< new 14.2 mss_thermal_init - exp_mss_thermal_init() - p9a_throttle_sync() <<< current place, stays here but also called earlier Change-Id: Iebf4ccb0f8b3f84ca146314b2a5d94ccbe88fc06 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88118 Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Corey V Swenson <cswenson@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G Hoffa <wghoffa@us.ibm.com>
open-power · Jan 7, 2020 · ddad6a5 · ddad6a5
1 parent a4f8acb
commit ddad6a5
Show file tree

Hide file tree

Showing 5 changed files with 64 additions and 7 deletions.
diff --git a/src/include/usr/isteps/istep13list.H b/src/include/usr/isteps/istep13list.H
@@ -295,6 +295,7 @@ const DepModInfo g_istep13Dependancies = {
         DEP_LIB(libistep13.so),
         DEP_LIB(libisteps_mss.so),
         DEP_LIB(libcen.so),
+        DEP_LIB(libnestmemutils.so),
         NULL
     }
 };

diff --git a/src/usr/hwplibs/nest/nestmemutils.mk b/src/usr/hwplibs/nest/nestmemutils.mk
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2017,2018
+# Contributors Listed Below - COPYRIGHT 2017,2019
 # [+] International Business Machines Corp.
 #
 #
@@ -26,15 +26,26 @@
 ROOTPATH=../../../..
 
 
+P9_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9/procedures/
 HWP_NEST_MEM_UTILS_PATH := ${ROOTPATH}/src/import/chips/p9/procedures/hwp/nest/
+EXP_COMMON_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/common
+AXONE_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9a/procedures
 
 EXTRAINCDIR += ${HWP_NEST_MEM_UTILS_PATH}
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/
 EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs
+EXTRAINCDIR += ${EXP_COMMON_PATH}/include/
+EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/
+EXTRAINCDIR += ${ROOTPATH}/src/import/
+EXTRAINCDIR += ${AXONE_PROCEDURE_PATH}/hwp/memory/
+EXTRAINCDIR += ${P9_PROCEDURE_PATH}/hwp/memory
 
 VPATH += ${HWP_NEST_MEM_UTILS_PATH}
 
 include ${ROOTPATH}/procedure.rules.mk
 
 include ${HWP_NEST_MEM_UTILS_PATH}/p9_putmemproc.mk
+OBJS += $(if $(CONFIG_AXONE),p9a_throttle_sync.o,p9_throttle_sync.o)
+
+include ${ROOTPATH}/config.mk
diff --git a/src/usr/isteps/istep13/call_mss_scominit.C b/src/usr/isteps/istep13/call_mss_scominit.C
@@ -42,12 +42,12 @@
 #include    <config.h>
 #include    <fapi2.H>
 #include    <p9_mss_scominit.H>
-#include    <p9_throttle_sync.H>
 #ifdef CONFIG_AXONE
-#include    <exp_scominit.H>
-#include    <chipids.H> // for EXPLORER ID
+  #include    <exp_scominit.H>
+  #include    <chipids.H> // for EXPLORER ID
+  #include    <p9a_throttle_sync.H>
 #else
-#include    <p9c_mss_scominit.H>
+  #include    <p9c_mss_scominit.H>
 #endif
 
 using   namespace   ERRORLOG;
@@ -264,6 +264,53 @@ void axone_call_mss_scominit(IStepError & io_istepError)
                   "target HUID %.8X", TARGETING::get_huid(l_ocmb_target));
         }
     }
+
+    // Need to setup the memory throttles for worstcase mode until
+    //  we get the thermals really setup later
+
+    // Get all functional proc chip targets
+    // Use targeting code to get a list of all processors
+    TARGETING::TargetHandleList l_procChips;
+    getAllChips( l_procChips, TARGETING::TYPE_PROC );
+
+    for (const auto & l_procChip: l_procChips)
+    {
+        //Convert the TARGETING::Target into a fapi2::Target by passing
+        //l_procChip into the fapi2::Target constructor
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
+          l_fapi2CpuTarget((l_procChip));
+
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "Running p9a_throttle_sync HWP on target HUID %.8X",
+                   TARGETING::get_huid(l_procChip) );
+        FAPI_INVOKE_HWP( l_err, p9a_throttle_sync, l_fapi2CpuTarget );
+
+        if (l_err)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                      "ERROR 0x%.8X: p9_throttle_sync HWP returns error",
+                      l_err->reasonCode());
+
+            // Capture the target data in the elog
+            ErrlUserDetailsTarget(l_procChip).addToLog(l_err);
+
+            // Create IStep error log and cross reference
+            //  to error that occurred
+            io_istepError.addErrorDetails( l_err );
+
+            // Commit Error
+            errlCommit( l_err, HWPF_COMP_ID );
+
+            break;
+        }
+        else
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                       "SUCCESS : p9_throttle_sync HWP on 0x%.8X processor",
+                       TARGETING::get_huid(l_procChip) );
+        }
+    }
+
 }
 #else
 void axone_call_mss_scominit(IStepError & io_istepError)

diff --git a/src/usr/isteps/istep13/makefile b/src/usr/isteps/istep13/makefile
@@ -97,7 +97,6 @@ include ${P9_PROCEDURES_PATH}/hwp/perv/p9_mem_startclocks.mk
 
 #Scom init
 include ${P9_PROCEDURES_PATH}/hwp/memory/p9_mss_scominit.mk
-include ${P9_PROCEDURES_PATH}/hwp/nest/p9_throttle_sync.mk
 OBJS += $(if $(CONFIG_AXONE),,p9c_mss_scominit.o)
 
 include ${P9_PROCEDURES_PATH}/hwp/initfiles/p9n_ddrphy_scom.mk

diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile
@@ -113,7 +113,6 @@ VPATH    += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/
 
 # Axone vs non-Axone specific HWP
 VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},)
-OBJS += $(if $(CONFIG_AXONE),p9a_throttle_sync.o,p9_throttle_sync.o)
 OBJS += $(if $(CONFIG_AXONE),exp_mss_thermal_init.o,)
 # TODO RTC:245219
 # use PRD's version of memdiags instead of this cronus verison once its working