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Fixes DD2 training bug
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In DD2 hardware, certain DIMMs were failing in training.
The fix was shown to be re-resetting the DRAM post RCWs.

Change-Id: I501c26c53b7a771f8a9dd8c4dff31f49d36d3758
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42222
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42224
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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sglancy6 authored and crgeddes committed Jun 23, 2017
1 parent fa9c9af commit e25076a
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64 changes: 36 additions & 28 deletions src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
#include <mss.H>
#include <lib/dimm/rcd_load_ddr4.H>
#include <lib/dimm/ddr4/control_word_ddr4.H>
#include <lib/workarounds/draminit_workarounds.H>

using fapi2::TARGET_TYPE_MCBIST;
using fapi2::TARGET_TYPE_MCA;
Expand Down Expand Up @@ -67,46 +68,53 @@ fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
// RCD 4-bit data - integral represents rc#
static const std::vector< cw_data > l_rcd_4bit_data =
{
{ FS0, 0, eff_dimm_ddr4_rc00, mss::tmrd() },
{ FS0, 1, eff_dimm_ddr4_rc01, mss::tmrd() },
{ FS0, 2, eff_dimm_ddr4_rc02, tSTAB },
{ FS0, 3, eff_dimm_ddr4_rc03, mss::tmrd_l() },
{ FS0, 4, eff_dimm_ddr4_rc04, mss::tmrd_l() },
{ FS0, 5, eff_dimm_ddr4_rc05, mss::tmrd_l() },
{ FS0, 0, eff_dimm_ddr4_rc00, mss::tmrd() },
{ FS0, 1, eff_dimm_ddr4_rc01, mss::tmrd() },
{ FS0, 2, eff_dimm_ddr4_rc02, tSTAB },
{ FS0, 3, eff_dimm_ddr4_rc03, mss::tmrd_l() },
{ FS0, 4, eff_dimm_ddr4_rc04, mss::tmrd_l() },
{ FS0, 5, eff_dimm_ddr4_rc05, mss::tmrd_l() },
// Note: the tMRC1 timing as it is larger for saftey's sake
// The concern is that if geardown mode is ever required in the future, we would need the longer timing
{ FS0, 6, eff_dimm_ddr4_rc06_07, mss::tmrc1() },
{ FS0, 8, eff_dimm_ddr4_rc08, mss::tmrd() },
{ FS0, 9, eff_dimm_ddr4_rc09, mss::tmrd() },
{ FS0, 10, eff_dimm_ddr4_rc0a, tSTAB },
{ FS0, 11, eff_dimm_ddr4_rc0b, mss::tmrd_l() },
{ FS0, 12, eff_dimm_ddr4_rc0c, mss::tmrd() },
{ FS0, 13, eff_dimm_ddr4_rc0d, mss::tmrd_l2() },
{ FS0, 14, eff_dimm_ddr4_rc0e, mss::tmrd() },
{ FS0, 15, eff_dimm_ddr4_rc0f, mss::tmrd_l2() },
{ FS0, 6, eff_dimm_ddr4_rc06_07, mss::tmrc1() },
{ FS0, 8, eff_dimm_ddr4_rc08, mss::tmrd() },
{ FS0, 9, eff_dimm_ddr4_rc09, mss::tmrd() },
{ FS0, 10, eff_dimm_ddr4_rc0a, tSTAB },
{ FS0, 11, eff_dimm_ddr4_rc0b, mss::tmrd_l() },
{ FS0, 12, eff_dimm_ddr4_rc0c, mss::tmrd() },
{ FS0, 13, eff_dimm_ddr4_rc0d, mss::tmrd_l2() },
{ FS0, 14, eff_dimm_ddr4_rc0e, mss::tmrd() },
{ FS0, 15, eff_dimm_ddr4_rc0f, mss::tmrd_l2() },
};

// RCD 8-bit data - integral represents rc#
static const std::vector< cw_data > l_rcd_8bit_data =
{
{ FS0, 1, eff_dimm_ddr4_rc_1x, mss::tmrd() },
{ FS0, 2, eff_dimm_ddr4_rc_2x, mss::tmrd() },
{ FS0, 3, eff_dimm_ddr4_rc_3x, tSTAB },
{ FS0, 4, eff_dimm_ddr4_rc_4x, mss::tmrd() },
{ FS0, 5, eff_dimm_ddr4_rc_5x, mss::tmrd() },
{ FS0, 6, eff_dimm_ddr4_rc_6x, mss::tmrd() },
{ FS0, 7, eff_dimm_ddr4_rc_7x, mss::tmrd_l() },
{ FS0, 8, eff_dimm_ddr4_rc_8x, mss::tmrd() },
{ FS0, 9, eff_dimm_ddr4_rc_9x, mss::tmrd() },
{ FS0, 10, eff_dimm_ddr4_rc_ax, mss::tmrd() },
{ FS0, 11, eff_dimm_ddr4_rc_bx, mss::tmrd_l() }
{ FS0, 1, eff_dimm_ddr4_rc_1x, mss::tmrd() },
{ FS0, 2, eff_dimm_ddr4_rc_2x, mss::tmrd() },
{ FS0, 3, eff_dimm_ddr4_rc_3x, tSTAB },
{ FS0, 4, eff_dimm_ddr4_rc_4x, mss::tmrd() },
{ FS0, 5, eff_dimm_ddr4_rc_5x, mss::tmrd() },
{ FS0, 6, eff_dimm_ddr4_rc_6x, mss::tmrd() },
{ FS0, 7, eff_dimm_ddr4_rc_7x, mss::tmrd_l() },
{ FS0, 8, eff_dimm_ddr4_rc_8x, mss::tmrd() },
{ FS0, 9, eff_dimm_ddr4_rc_9x, mss::tmrd() },
{ FS0, 10, eff_dimm_ddr4_rc_ax, mss::tmrd() },
{ FS0, 11, eff_dimm_ddr4_rc_bx, mss::tmrd_l() },
};

// Load 4-bit data
FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, io_inst) );
FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, io_inst), "%s failed to load 4-bit control words",
mss::c_str(i_target));

// Load 8-bit data
FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, io_inst) );
FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, io_inst), "%s failed to load 8-bit control words",
mss::c_str(i_target));

// DD2 hardware has an issue with properly resetting the DRAM
// The below workaround toggles RC06 again to ensure the DRAM is reset properly
FAPI_TRY( mss::workarounds::rcw_reset_dram(i_target, io_inst), "%s failed to add reset workaround functionality",
mss::c_str(i_target));

fapi_try_exit:
return fapi2::current_err;
Expand Down
60 changes: 60 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C
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Original file line number Diff line number Diff line change
Expand Up @@ -22,3 +22,63 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */

///
/// @file workarounds/draminit_workarounds.C
/// @brief Workarounds for the draminit code
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB

#include <fapi2.H>

#include <mss.H>
#include <lib/dimm/rcd_load_ddr4.H>
#include <lib/dimm/ddr4/control_word_ddr4.H>
#include <lib/workarounds/draminit_workarounds.H>

namespace mss
{

namespace workarounds
{

///
/// @brief Runs the DRAM reset workaround to fix training bugs
/// @param[in] i_target - the target on which to operate
/// @param[in,out] a vector of CCS instructions we should add to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode rcw_reset_dram( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst)
{
// Note: we're always going to run this guy
FAPI_INF("%s running the DRAM RCW DRAM reset workaround", mss::c_str(i_target));

// Declares constexpr's
constexpr uint64_t RESET_CW = 6;
constexpr uint64_t RESET_DRAM = 0x02;
constexpr uint64_t CLEAR_RESET = 0x03;
// Using a delay of 2000 cycles to ensure we're holding everything for a long enough time
// Note: this value is set using "engineering judgement" and was considered arbitrarily high enough
constexpr uint64_t DELAY = 2000;
// Function space 0
constexpr uint8_t FS0 = 0;

// Reset, then clear the data
static const std::vector< cw_data > l_rcd_reset_data =
{
{ FS0, RESET_CW, RESET_DRAM, DELAY },
{ FS0, RESET_CW, CLEAR_RESET, DELAY },
};

// Load the data into the CCS array
return control_word_engine<RCW_4BIT>(i_target, l_rcd_reset_data, io_inst);
}

} // namespace workarounds

} // namespace mss
35 changes: 35 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H
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Original file line number Diff line number Diff line change
Expand Up @@ -22,3 +22,38 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */

///
/// @file workarounds/draminit_workarounds.H
/// @brief Workarounds for the draminit code
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB

#include <fapi2.H>

#include <mss.H>
#include <lib/dimm/rcd_load_ddr4.H>
#include <lib/dimm/ddr4/control_word_ddr4.H>

namespace mss
{

namespace workarounds
{

///
/// @brief Runs the DRAM reset workaround to fix training bugs
/// @param[in] i_target - the target on which to operate
/// @param[in,out] a vector of CCS instructions we should add to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode rcw_reset_dram( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst);

} // namespace workarounds

} // namespace mss

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