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Add OMI training hang workaround
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Change-Id: Ie63fae36552e9ab0228c68dd945aae21d21968bf
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/95523
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/95551
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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@markypizz @dcrowell77
markypizz authored and dcrowell77 committed May 5, 2020
1 parent 3e8d0ec commit e45676f
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Showing 5 changed files with 121 additions and 15 deletions.
18 changes: 6 additions & 12 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.C
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Expand Up @@ -53,9 +53,6 @@ fapi2::ReturnCode exp_omi_train_check(const fapi2::Target<fapi2::TARGET_TYPE_OCM

FAPI_INF("%s Start exp_omi_train_check", mss::c_str(i_target));

// Const
constexpr uint8_t STATE_MACHINE_SUCCESS = 0b111; // This value is from Lonny Lambrecht
constexpr uint8_t MAX_LOOP_COUNT = 10; // Retry times
const auto& l_omi = mss::find_target<fapi2::TARGET_TYPE_OMI>(i_target);
const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target);

Expand All @@ -66,20 +63,17 @@ fapi2::ReturnCode exp_omi_train_check(const fapi2::Target<fapi2::TARGET_TYPE_OCM
fapi2::buffer<uint64_t> l_expected_dl0_error_hold;
fapi2::buffer<uint64_t> l_dl0_config1;
uint8_t l_state_machine_state = 0;
uint8_t l_tries = 0;
uint32_t l_omi_freq = 0;

do
{
// Delay
fapi2::delay(500 * mss::DELAY_1MS, 10 * mss::DELAY_1MS);
FAPI_TRY(mss::exp::omi::train::poll_for_training_completion(i_target, l_state_machine_state, l_omi_status));

// Check OMI training status
FAPI_TRY(mss::exp::omi::train::omi_train_status(i_target, l_state_machine_state, l_omi_status));
l_tries++;
if (l_state_machine_state == mss::omi::train_mode::TX_TRAINING_STATE2)
{
FAPI_TRY(mss::exp::omi::train::bump_sl_workaround(l_omi));

// Now poll once more
FAPI_TRY(mss::exp::omi::train::poll_for_training_completion(i_target, l_state_machine_state, l_omi_status));
}
while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS);

// Note: this is very useful debug information while trying to debug training during polling
FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_TRAINING_STATUS, l_omi_training_status));
Expand Down
87 changes: 86 additions & 1 deletion src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C
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Expand Up @@ -42,7 +42,11 @@
#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
#include <lib/shared/exp_consts.H>

static constexpr uint8_t OPTIMAL_NUM_TL_CREDITS = 18;
// P9 cross-includes
#include <p9_io_scom.H>
#include <p9_io_regs.H>
#include <p9a_mc_scom_addresses.H>
#include <p9a_mc_scom_addresses_fld.H>

namespace mss
{
Expand Down Expand Up @@ -181,6 +185,87 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Helper function to perform BUMP_SL workaround
///
/// @param[in] i_omi OMI target
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
///
fapi2::ReturnCode bump_sl_workaround(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi)
{
FAPI_DBG("Performing BUMP_SL workaround on %s", mss::c_str(i_omi));

const auto& l_omic = mss::find_target<fapi2::TARGET_TYPE_OMIC>(i_omi);

fapi2::buffer<uint64_t> l_omi_status;
uint8_t l_state_machine_state_omi = 0;

// Check OMI training status
FAPI_TRY(mss::getScom(i_omi, P9A_MC_REG2_DL0_STATUS, l_omi_status));
l_omi_status.extractToRight<P9A_MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE,
P9A_MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN>(l_state_machine_state_omi);

if (l_state_machine_state_omi == mss::omi::train_mode::TX_TRAINING_STATE1)
{
// Perform the real workaround
uint8_t l_group_pos = 0;
uint32_t l_lane = 0;

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OMI_DL_GROUP_POS, i_omi, l_group_pos));

l_lane = l_group_pos * mss::conversions::BITS_PER_BYTE; // tk 8 = bits_per_byte

// Set
FAPI_TRY(io::rmw(OPT_RX_PR_BUMP_SL_1UI, // reg, fld, len
l_omic, // target
0, // group
l_lane, // lane
1)); // data

// Reset
FAPI_TRY(io::rmw(OPT_RX_PR_BUMP_SL_1UI, // reg, fld, len
l_omic, // target
0, // group
l_lane, // lane
0)); // data
}

fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Poll for OMI training completion
///
/// @param[in] i_target OCMB target
/// @param[out] o_state_machine_state state machine state
/// @param[out] o_omi_status omi status register buffer
/// @return fapi2::ReturnCode
///
fapi2::ReturnCode poll_for_training_completion(
const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
uint8_t& o_state_machine_state,
fapi2::buffer<uint64_t>& o_omi_status)
{
constexpr uint8_t MAX_LOOP_COUNT = 10; // Retry times
uint8_t l_tries = 0;

do
{
// Delay
fapi2::delay(500 * mss::DELAY_1MS, 10 * mss::DELAY_1MS);

// Check OMI training status
FAPI_TRY(mss::exp::omi::train::omi_train_status(i_target, o_state_machine_state, o_omi_status));
l_tries++;

}
while (l_tries < MAX_LOOP_COUNT && o_state_machine_state != STATE_MACHINE_SUCCESS);

fapi_try_exit:
return fapi2::current_err;
}

} // ns train

} // ns omi
Expand Down
26 changes: 25 additions & 1 deletion src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* Contributors Listed Below - COPYRIGHT 2018,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -40,6 +40,9 @@
#include <explorer_scom_addresses_fld.H>
#include <generic/memory/lib/utils/c_str.H>

static constexpr uint8_t OPTIMAL_NUM_TL_CREDITS = 18;
static constexpr uint8_t STATE_MACHINE_SUCCESS = 0b111; // This value is from Lonny Lambrecht

namespace mss
{
namespace exp
Expand Down Expand Up @@ -243,6 +246,27 @@ fapi2::ReturnCode omi_train_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
uint8_t& o_state_machine_state,
fapi2::buffer<uint64_t>& o_omi_training_status);

///
/// @brief Helper function to perform BUMP_SL workaround
///
/// @param[in] i_omi OMI target
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
///
fapi2::ReturnCode bump_sl_workaround(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi);

///
/// @brief Poll for OMI training completion
///
/// @param[in] i_target OCMB target
/// @param[out] o_state_machine_state state machine state
/// @param[out] o_omi_status omi status register buffer
/// @return fapi2::ReturnCode
///
fapi2::ReturnCode poll_for_training_completion(
const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
uint8_t& o_state_machine_state,
fapi2::buffer<uint64_t>& o_omi_status);

} // ns train

} // ns omi
Expand Down
4 changes: 3 additions & 1 deletion src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* Contributors Listed Below - COPYRIGHT 2015,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -652,7 +652,9 @@
#define OPT_RX_PR_DDC_B 0x800248000000003f, 54, 1 // enables ddc state machine to go through its ddc routine on pr b. works by shifting to the left and right looking for errors to find the edges, then adds an offset that centers the data between the 2 edges.
#define OPT_RX_PR_BUMP_TO_EDGE_A 0x800248000000003f, 55, 1 // bumps pr a position to the edge => +(16 - clkadj).
#define OPT_RX_PR_BUMP_TO_EDGE_B 0x800248000000003f, 56, 1 // bumps pr b position to the edge. (not supported)
*/
#define OPT_RX_PR_BUMP_SL_1UI 0x800248000000003f, 57, 1 // bumps the pr position of all prs to the next eye by shifting 32-steps. (not supported)
/*
#define OPT_RX_PR_BUMP_SR_1UI 0x800248000000003f, 58, 1 // bumps the pr position to the previous eye by shifting 32-steps. (not supported)
#define OPT_RX_PR_DATA_OFFSET_DISABLE_A 0x800248000000003f, 59, 1 // disables phase rotator offset for a bank (dd2
#define OPT_RX_PR_DATA_OFFSET_DISABLE_B 0x800248000000003f, 60, 1 // disables phase rotator offset for b bank (dd2
Expand Down
1 change: 1 addition & 0 deletions src/usr/isteps/mss/makefile
View file
Expand Up @@ -60,6 +60,7 @@ MSS_LIB += ${PROCEDURES_PATH}/hwp/memory/lib/spd/
MSS_LIB += ${PROCEDURES_PATH}/hwp/memory/lib/utils/
MSS_LIB += ${PROCEDURES_PATH}/hwp/memory/lib/workarounds/
MSS_LIB += ${PROCEDURES_PATH}/hwp/memory/lib/rosetta_map/
MSS_LIB += ${PROCEDURES_PATH}/hwp/io/
MSS_LIB += ${ROOTPATH}/src/import/
MSS_LIB += ${ROOTPATH}/src/import/generic/memory/lib/spd/lrdimm/ddr4/
MSS_LIB += ${ROOTPATH}/src/import/generic/memory/lib/spd/rdimm/ddr4/
Expand Down

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